Integrated circuit package for flip chip

Claim 2

An integrated circuit package comprising: a ceramic substrate having opposing upper and lower sides and formed from a plurality of stacked ceramic layers having a cut out configured to receive a flip chip, said cut out including through holes extending through to the lower side of said ceramic substrate, wherein one of said stacked ceramic layers includes a metallized conductive pattern forming a grounding signal path located substantially medially within the ceramic substrate; a gallium arsenide integrated circuit flip chip received within the cut out of the ceramic substrate and having conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip, wherein the conductive bumps extend downward and are received within the through holes of the ceramic substrate; a controlled impedance line secured to the conductive bumps; a second integrated circuit chip mounted back-to-back on the flip chip received within the cut out, a conductive epoxy positioned between the flip chip and second integrated circuit chip and securing said chips to each other, wherein said conductive epoxy is connected to said grounding signal path for back-to-back grounding of said flip chip and second integrated circuit chip, said second integrated circuit chip including electrical contacts that are upward in direction; and a conductive pattern positioned on said upper side of said ceramic substrate and connected to said electrical contacts on said second integrated circuit chip.

Claim 3

A package according to claim 1 , wherein said conductive bumps are formed from gold.

Claim 4

A package according to claim 1 , and further comprising a conductive ink plated on the through holes.

Claim 5

A package according to claim 1 , and further comprising a means for adhesively securing said controlled impedance line to the conductive bumps.

Claim 6

A package according to claim 1 , and further comprising a second stepped cut out for receiving the second integrated circuit chip.

Claim 7

A package according to claim 1 , wherein said conductive bumps are formed of epoxy having a conductive material impregnated therein.

Claim 8

An integrated circuit package comprising: a ceramic substrate having opposing upper and lower sides and formed from a plurality of stacked ceramic layers and having conductive patterns formed on the upper side thereon, and a cut out configured to receive a flip chip, said cut out including through holes extending through to the lower side of said ceramic substrate, and a metallized conductive pattern located substantially medially within the ceramic substrate and on one of said stacked ceramic layers and forming a grounding signal path a gallium arsenide integrated circuit flip chip received within the cut out of the ceramic substrate and having conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip, wherein the conductive bumps are downward received within the through holes of the ceramic substrate; a controlled impedance line secured to the conductive bumps; an electrically conductive heat sink mounted on the flip chip; a second integrated circuit chip mounted on the heat sink in back-to-back relationship to the flip chip, and including electrical contacts, such that the electrical contacts of the second integrated circuit chip are upward in direction, wherein said flip chip and second integrated circuit chip are adhesively secured to said electrically conductive heat sink by an electrically conductive adhesive to allow back-to-back grounding, and wherein said conductive epoxy is connected to said grounding signal path for back-to-back grounding of said flip chip and said second integrated circuit chip; and means for electrically connecting the electrical contacts of the second integrated circuit to said conductive patterns formed on the upper side of the ceramic substrate.

Claim 9

An integrated circuit package comprising: a ceramic substrate having opposing upper and lower sides and formed from a plurality of stacked ceramic layers and having conductive patterns formed on the upper side thereon, and a cut out configured to receive a flip chip, said cut out including through holes extending through to the lower side of said ceramic substrate, and a metallized conductive pattern located substantially medially within the ceramic substrate and on one of said stacked ceramic layers and forming a grounding signal path a gallium arsenide integrated circuit flip chip received within the cut out of the ceramic substrate and having conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip, wherein the conductive bumps are downward received within the through holes of the ceramic substrate; a controlled impedance line secured to the conductive bumps; an electrically conductive heat sink mounted on the flip chip; a second integrated circuit chip mounted on the heat sink in back-to-back relationship to the flip chip, and including electrical contacts, such that the electrical contacts of the second integrated circuit chip are upward in direction, wherein said flip chip and second integrated circuit chip are adhesively secured to said electrically conductive heat sink by an electrically conductive adhesive to allow back-to-back grounding, and wherein said conductive epoxy is connected to said grounding signal path for back-to-back grounding of said flip chip and said second integrated circuit chip; and means for electrically connecting the electrical contacts of the second integrated circuit to said conductive patterns formed on the upper side of the ceramic substrate.

Claim 10

A package according to claim 7 , wherein said conductive bumps are formed from gold.

Claim 11

A package according to claim 7 , and further comprising a conductive ink plated on the through holes.

Claim 12

A package according to claim 7 , and further comprising a controlled impedance line secured to the conductive bumps.

Claim 13

A package according to claim 7 , and further comprising a stepped cut out formed in the ceramic substrate for receiving the flip chip and the second integrated circuit chip.

Claim 14

A package according to claim 7 , wherein said conductive bumps are formed as epoxy having a conductive material impregnated therein.

Claim 15

A package according to claim 7 , and further comprising a conductive epoxy that secures together the flip chip, heat sink and second integrated circuit.