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US5925934A Expired / Lapsed US ⏱️ 0.0 years remaining

Low cost and highly reliable chip-sized package

Assignee: Institute of Microelectronics
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Filing: 1996-01-04
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Granted: 1999-07-20
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Expires: 2016-01-04
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Abstract

Abstract The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports. Alternatively, prior to encapsulation, the chip ports are positioned to sit on a mold, so that removing the mold leaves exposed the portions of the chip ports that were in contact with the mold. The mold may have an array of mold bumps or mold pockets upon which the chip ports sit. Removing the mold, exposes portions of the chip ports and leaves an array of openings in the encapsulant. Another method to form the array of openings in the encapsulant and expose portions of the chip ports uses an array of pins that are inserted in the encapsulant before it cures. The pins are inserted to contact the chip ports. Retracting the array of pins forms the array of openings in the encapsulant and exposes portions of the chip ports that were in contact with the pins.

Inventors

  • 👤 Thiam Beng Lim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 20:13
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W74/01; H10W74/016; H10W72/00; H10W72/071; H10W72/073; H10W72/851; H10W72/874; H10W72/884; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 112 words
A chip-sized package comprising: a chip having an active surface; chip ports arranged in an array on said active surface; an encapsulant which encapsulates said chip and portions of said chip ports located nearest said active surface, portions of said chip ports which are located away from said active surface being exposed from said encapsulant; a package port attached to the exposed portions of each chip port, wherein each package port is electrically connectable to a circuit board; at least two frame tie-bars positioned opposite each other and not extending entirely across a surface of the chip; and a die attach which attaches the chip to the at least two frame tie-bars.
Claim 2
Dependent Claim 112 words
A chip-sized package comprising: a chip having an active surface; chip ports arranged in an array on said active surface; an encapsulant which encapsulates said chip and portions of said chip ports located nearest said active surface, portions of said chip ports which are located away from said active surface being exposed from said encapsulant; a package port attached to the exposed portions of each chip port, wherein each package port is electrically connectable to a circuit board; at least two frame tie-bars positioned opposite each other and not extending entirely across a surface of the chip; and a die attach which attaches the chip to the at least two frame tie-bars.
Claim 3
Dependent Claim 22 words
The chip-sized package of claim 1, wherein said frame tie-bar and said array chip ports are on opposite surfaces of said chip.
Claim 4
Dependent Claim 14 words
The chip-sized package of claim 1, wherein said encapsulant is an epoxy molding compound.
Claim 5
Dependent Claim 20 words
The chip-sized package of claim 1, wherein said array of chip ports comprises an array of conductive bumps or balls.
Claim 6
Dependent Claim 18 words
The chip-sized package of claim 1, wherein said array of chip ports comprises an array of metal bumps.
Claim 7
Dependent Claim 21 words
The chip-sized package of claim 1, wherein said array of chip ports comprises an array of conductive polymer bumps or balls.
Claim 8
Dependent Claim 18 words
The chip-sized package of claim 1, wherein said array of chip ports is an array of solder bumps.
Claim 9
Dependent Claim 21 words
The chip-sized package of claim 1, wherein said array of package ports is an array of conductive polymer bumps or balls.
Claim 10
Dependent Claim 20 words
The chip-sized package of claim 1, wherein said array of package ports is an array of solder bumps or balls.
Claim 11
Dependent Claim 19 words
The chip-sized package of claim 1, wherein the frame tie-bars are connected to an inactive surface of the chip.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-07-19 2003-01-18 2003-07-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-07-19 2007-01-18 2007-07-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-07-19 2011-01-18 2011-07-20 $7700.00 Window Closed / Lapsed

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