US6172937B1
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Multiple synthesizer based timing signal generation scheme
Assignee: Intel Corp
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Filing: 1999-05-10
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Granted: 2001-01-09
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Expires: 2019-05-10
Abstract
Abstract A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
Inventors
- 👤 Alper Ilkbahar
- 👤 Simon M. Tam
- 👤 Ian A. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:51
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/06
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
118 words
A circuit comprising: a primary clock synthesizer coupled to receive a system clock signal, the primary clock synthesizer to generate a core clock signal; bus clock generation logic coupled to the primary clock synthesizer, the bus clock generation logic to generate a bus clock signal based, at least in part, on the core clock signal; a secondary clock synthesizer coupled to the bus clock generation logic, the secondary clock synthesizer to generate a secondary clock signal based, at least in part, on the bus clock signal; and strobe signal generation logic coupled to the secondary clock synthesizer, the strobe signal generation logic to generate a strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 2
Dependent Claim
118 words
A circuit comprising: a primary clock synthesizer coupled to receive a system clock signal, the primary clock synthesizer to generate a core clock signal; bus clock generation logic coupled to the primary clock synthesizer, the bus clock generation logic to generate a bus clock signal based, at least in part, on the core clock signal; a secondary clock synthesizer coupled to the bus clock generation logic, the secondary clock synthesizer to generate a secondary clock signal based, at least in part, on the bus clock signal; and strobe signal generation logic coupled to the secondary clock synthesizer, the strobe signal generation logic to generate a strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein the primary clock synthesizer comprises a phase locked loop (PLL) device.
Claim 4
Dependent Claim
17 words
The circuit of claim 1 wherein the primary clock synthesizer comprises a delay locked loop (DLL) device.
Claim 5
Dependent Claim
17 words
The circuit of claim 1 wherein the secondary clock synthesizer comprises a phase locked loop (PLL) device.
Claim 6
Dependent Claim
17 words
The circuit of claim 1 wherein the secondary clock synthesizer comprises a delay locked loop (DLL) device.
Claim 7
Dependent Claim
34 words
The circuit of claim 1 further comprising a clock ratio logic coupled to receive the core clock signal, the clock ratio logic to control the ratio of the core clock to the system clock.
Claim 8
Dependent Claim
20 words
The circuit of claim 1 wherein the bus clock signal frequency is substantially equal to the system clock signal frequency.
Claim 9
Dependent Claim
21 words
The circuit of claim 1 wherein the secondary clock signal frequency is an even multiple of the bus clock signal frequency.
Claim 10
Dependent Claim
46 words
The circuit of claim 1 further comprising data output logic to output data on alternating transitions of the secondary clock signal, wherein the transitions of the strobe signal occur approximately midway between the alternating transitions of the secondary clock signal on which the data is output.
Claim 11
Independent Claim
91 words
An apparatus for generating clock signals, the apparatus comprising: means for generating a core clock signal based, at least in part, on a system clock signal; means for generating a bus clock signal based, at least in part, on the core clock signal; means for generating a secondary clock signal based, at least in part, on the bus clock signal; and means for generating a strobe signal based, at least in part, on the secondary clock signal, the strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 12
Independent Claim
91 words
An apparatus for generating clock signals, the apparatus comprising: means for generating a core clock signal based, at least in part, on a system clock signal; means for generating a bus clock signal based, at least in part, on the core clock signal; means for generating a secondary clock signal based, at least in part, on the bus clock signal; and means for generating a strobe signal based, at least in part, on the secondary clock signal, the strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 13
Dependent Claim
22 words
The apparatus of claim 10 further comprising means for controlling a ratio between the core clock signal and the system clock signal.
Claim 14
Dependent Claim
20 words
The apparatus of claim 10 wherein the strobe signal has transitions corresponding to alternating transitions of the secondary clock signal.
Claim 15
Dependent Claim
40 words
The apparatus of claim 10 further comprising means for outputting data on alternating transitions of the secondary clock signal, wherein transitions of the strobe signal occur approximately midway between transitions of the secondary clock signal on which data is output.
Claim 16
Independent Claim
83 words
A method of generating clock signals, the method comprising: generating a core clock signal based, at least in part, on a system clock signal; generating a bus clock signal based, at least in part, on the core clock signal; generating a secondary clock signal based, at least in part, on the bus clock signal; and generating a strobe signal based, at least in part, on the secondary clock signal, the strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 17
Independent Claim
83 words
A method of generating clock signals, the method comprising: generating a core clock signal based, at least in part, on a system clock signal; generating a bus clock signal based, at least in part, on the core clock signal; generating a secondary clock signal based, at least in part, on the bus clock signal; and generating a strobe signal based, at least in part, on the secondary clock signal, the strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 18
Dependent Claim
20 words
The method of claim 14 wherein the strobe signal has transitions corresponding to alternating transitions of the secondary clock signal.
Claim 19
Dependent Claim
38 words
The method of claim 14 further comprising outputting data on alternating transitions of the secondary clock signal, wherein transitions of the strobe signal occur approximately midway between transitions of the secondary clock signal on which data is output.
Claim 20
Dependent Claim
29 words
The method of claim 14 wherein generating the core clock signal comprises providing the system clock signal to a phase locked loop (PLL) to generate the core clock signal.
Claim 21
Dependent Claim
29 words
The method of claim 14 wherein generating the core clock signal comprises providing the system clock signal to a delay locked loop (DLL) to generate the core clock signal.
Claim 22
Dependent Claim
29 words
The method of claim 14 wherein generating the secondary clock signal comprises providing the bus clock signal to a phase locked loop (PLL) to generate the secondary clock signal.
Claim 23
Dependent Claim
29 words
The method of claim 14 wherein generating the secondary clock signal comprises providing the bus clock signal to a delay locked loop (DLL) to generate the secondary clock signal.
Claim 24
Dependent Claim
87 words
A circuit comprising: a primary clock synthesizer coupled to receive a system clock signal, the primary clock synthesizer to generate a core clock signal; a secondary clock synthesizer coupled to receive the system clock signal, the secondary clock synthesizer to generate a secondary clock signal based, at least in part, on the bus clock signal; and strobe signal generation logic coupled to the secondary clock synthesizer, the strobe signal generation logic to generate a strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 25
Dependent Claim
87 words
A circuit comprising: a primary clock synthesizer coupled to receive a system clock signal, the primary clock synthesizer to generate a core clock signal; a secondary clock synthesizer coupled to receive the system clock signal, the secondary clock synthesizer to generate a secondary clock signal based, at least in part, on the bus clock signal; and strobe signal generation logic coupled to the secondary clock synthesizer, the strobe signal generation logic to generate a strobe signal having transitions corresponding to alternate transitions of the secondary clock signal.
Claim 26
Dependent Claim
17 words
The circuit of claim 21 wherein the primary clock synthesizer comprises a phase locked loop (PLL) device.
Claim 27
Dependent Claim
17 words
The circuit of claim 21 wherein the primary clock synthesizer comprises a delay locked loop (DLL) device.
Claim 28
Dependent Claim
17 words
The circuit of claim 21 wherein the secondary clock synthesizer comprises a phase locked loop (PLL) device.
Claim 29
Dependent Claim
17 words
The circuit of claim 21 wherein the secondary clock synthesizer comprises a delay locked loop (DLL) device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |