US5949262A
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US
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Method and apparatus for coupled phase locked loops
Assignee: International Business Machines Corp
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Filing: 1998-01-07
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Granted: 1999-09-07
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Expires: 2018-01-07
Abstract
Abstract A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.
Inventors
- 👤 Daniel Mark Dreps
- 👤 Robert Paul Masleid
- 👤 John Stephen Muhich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:29
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H04; H04L; H04L7/00; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
108 words
A method for generating synchronized clock signals, comprising the steps of: a) generating first and second pluralities of signals, having time-varying phase differences with respect to a reference clock signal; b) supplying a first clock signal by a first succession of signals from among the first plurality of signals, wherein the signals succeed one another responsive to a first phase difference; and c) supplying a second clock signal by a second succession of signals from among the second plurality of signals, wherein the signals succeed one another responsive to a second phase difference, and wherein the first succession of signals is also responsive to the second phase difference.
Claim 2
Independent Claim
108 words
A method for generating synchronized clock signals, comprising the steps of: a) generating first and second pluralities of signals, having time-varying phase differences with respect to a reference clock signal; b) supplying a first clock signal by a first succession of signals from among the first plurality of signals, wherein the signals succeed one another responsive to a first phase difference; and c) supplying a second clock signal by a second succession of signals from among the second plurality of signals, wherein the signals succeed one another responsive to a second phase difference, and wherein the first succession of signals is also responsive to the second phase difference.
Claim 3
Dependent Claim
37 words
The method of claim 1, wherein for the first succession of signals, the succession of one of the signals by another one of the signals is responsive to the second phase difference being in a first direction.
Claim 4
Dependent Claim
37 words
The method of claim 2, wherein for the second succession of signals, the succession of one of the signals by another one of the signals is responsive to the second phase difference being in a second direction.
Claim 5
Dependent Claim
24 words
The method of claim 1, wherein the first phase difference is a phase difference between the first clock signal and the reference clock signal.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein the second phase difference is a phase difference between the first clock signal and the second clock signal.
Claim 7
Independent Claim
154 words
An apparatus for generating synchronized clock signals, comprising: a) first signal source for generating first plurality of signals, having time-varying phase differences with respect to a reference clock signal; b) second signal source for generating second plurality of signals, having time-varying phase differences with respect to the reference clock signal; c) first phase detector, responsive to a first phase difference, for supplying a first control signal, wherein the first signal source, responsive to the first control signal, supplies a first clock signal by a first succession of signals from among the first plurality of signals; and d) second phase detector, responsive to a second phase difference, for supplying a second control signal, wherein the second signal source, responsive to the second control signal, supplies a second clock signal by a second succession of signals from among the second plurality of signals, wherein the first signal source is also responsive to the second phase difference.
Claim 8
Independent Claim
154 words
An apparatus for generating synchronized clock signals, comprising: a) first signal source for generating first plurality of signals, having time-varying phase differences with respect to a reference clock signal; b) second signal source for generating second plurality of signals, having time-varying phase differences with respect to the reference clock signal; c) first phase detector, responsive to a first phase difference, for supplying a first control signal, wherein the first signal source, responsive to the first control signal, supplies a first clock signal by a first succession of signals from among the first plurality of signals; and d) second phase detector, responsive to a second phase difference, for supplying a second control signal, wherein the second signal source, responsive to the second control signal, supplies a second clock signal by a second succession of signals from among the second plurality of signals, wherein the first signal source is also responsive to the second phase difference.
Claim 9
Dependent Claim
22 words
The apparatus of claim 6, wherein the first signal source is responsive to the second phase difference being in a first direction.
Claim 10
Dependent Claim
22 words
The apparatus of claim 6, wherein the second signal source is responsive to the second phase difference being in a second direction.
Claim 11
Dependent Claim
24 words
The apparatus of claim 6, wherein the first phase difference is a phase difference between the first clock signal and the reference clock signal.
Claim 12
Dependent Claim
24 words
The apparatus of claim 6, wherein the second phase difference is a phase difference between the first clock signal and the second clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |