Shifting the phase of a clock signal, in particular for clock recovery of a digital data signal

Claim 1

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said activating means include an analog control network and an analog selector, which both are connected for receiving the control signal, the control network controlling the selector for entirely opening, via one of the chosen control outputs, a corresponding switching means for letting through the corresponding auxiliary signal without amplitude decrease, and for connecting, via another chosen control output, the control signal with correct sign to a corresponding switching means for letting through the corresponding auxiliary clock signal with an amplitude decrease determined by the amplitude of the control signal.

Claim 2

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said activating means include an analog control network and an analog selector, which both are connected for receiving the control signal, the control network controlling the selector for entirely opening, via one of the chosen control outputs, a corresponding switching means for letting through the corresponding auxiliary signal without amplitude decrease, and for connecting, via another chosen control output, the control signal with correct sign to a corresponding switching means for letting through the corresponding auxiliary clock signal with an amplitude decrease determined by the amplitude of the control signal.

Claim 14

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 15

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 20

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry having as an input said control signal with a variable amplitude and sign, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 21

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including: a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, a control signal generator for providing a control signal with a variable amplitude and sign, and a selector circuit having a control input for receiving said control signal, control outputs for controlling the switching means to let through their respective auxiliary clock signals, and activating means for monitoring the amplitude and sign of said control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry having as an input said control signal with a variable amplitude and sign, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 30

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal, a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein the detector circuit creates and transmits the phase position information in the form of an analog signal, the amplitude of which is a measure of the magnitude of the phase error, and the sign of which indicates the direction of the phase error, and the activating means include an analog control network and an analog selector, which both are connected for receiving the analog signal, the control network controlling the selector to entirely open, via one of the two chosen control outputs, the corresponding switching means for letting through the auxiliary clock signal thereof without amplitude decrease, and to connect, via the other chosen control output, the analog signal with the correct sign to the corresponding switching means for letting through the auxiliary clock signal thereof with an amplitude decrease determined by the amplitude of the control signal.

Claim 31

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal, a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein the detector circuit creates and transmits the phase position information in the form of an analog signal, the amplitude of which is a measure of the magnitude of the phase error, and the sign of which indicates the direction of the phase error, and the activating means include an analog control network and an analog selector, which both are connected for receiving the analog signal, the control network controlling the selector to entirely open, via one of the two chosen control outputs, the corresponding switching means for letting through the auxiliary clock signal thereof without amplitude decrease, and to connect, via the other chosen control output, the analog signal with the correct sign to the corresponding switching means for letting through the auxiliary clock signal thereof with an amplitude decrease determined by the amplitude of the control signal.

Claim 37

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal, a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 38

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal, a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 43

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry having as an input said control signal with a variable amplitude and sign, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 44

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry having as an input said control signal with a variable amplitude and sign, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 54

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, means for providing control signals to said switching means; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 55

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, means for providing control signals to said switching means; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 60

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, means for providing control signals to said switching means; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 61

A system for shifting the phase of a clock signal, comprising: first means for receiving said clock signal and providing a number of auxiliary clock signals phase shifted with respect to said clock signal and to each other, second means for choosing two of the auxiliary clock signals between the phases of which a desired new phase of said clock signal is situated, and third means for mixing the two chosen auxiliary clock signals with each other until a signal with said desired phase is obtained, including a number of controllable switching means having auxiliary clock signal inputs for receiving said auxiliary clock signals, and a common output on which said signal with the desired phase is obtained, means for providing control signals to said switching means; wherein said controllable switching means comprise a number of sets of at least one differentially connected pair each of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said sets of pairs being further connected to said voltage source means via a number of digitally controllable current sources having control inputs connected to logic circuitry, and said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 66

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.

Claim 67

A system for clock recovery of a digital data signal, comprising: a phase detector for receiving the data signal and transmitting the same after clock recovery, a phase correcting device for creating and emitting, by means of a number of mutually phase shifted auxiliary signals derived from an incoming clock signal a recovered clock signal for the data signal, said recovered clock signal being fed to the phase detector for detecting a phase position error, if any, between the data signal and its recovered clock signal and transmitting information with respect to this to the phase correcting device, the phase correction device including; a phase variation circuit for mixing, if the phase position error is different from zero and the phase position of the recovered clock signal is situated between the phase position for two auxiliary clock signals, these two auxiliary clock signals being mixed with each other for forming an adjusted recovered clock signal having the same phase position as the data signal; wherein the phase variation circuit includes; a number of controllable switching means for receiving on auxiliary clock signal inputs said auxiliary clock signals and connected to a common output, on which the recovered clock signal with the shifted phase is obtained, and a selector circuit with control outputs connected for controlling the switch means to let through their respective auxiliary clock signals, and with activating means for monitoring the magnitude and sign of the control signal and selectively activating a number of the control outputs; wherein said controllable switching means comprise a number of differentially connected pairs of first and second controlled switches, said pairs being located between voltage source means and a common differential output having first and second terminals for forming said common output for said signal with the desired phase, said first and second controlled switches of each pair having respective outputs connected to said first and second terminals, respectively, said pairs being further connected to said voltage source means via current path means containing current source means and control means connected to said control outputs for controlling the current flow to said pairs, said controlled switches having control inputs connected for receiving said auxiliary clock signals.