US4419150A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming lateral bipolar transistors
Assignee: Conexant Systems LLC
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Filing: 1982-09-16
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Granted: 1983-12-06
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Expires: 2002-09-16
Abstract
Abstract The invention is a sub-micron dielectrically isolated transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by a field oxide region, N+ spaced-apart doped portions within said regions and a P+ doped portion of said region spaced from each N+ doped portions, and electrical connections to the base P+ portion and the collector and emitter N+ portions. These regions are established by first forming boundary recesses about each active portion where a transistor will be formed, depositing arsenic in the recesses to form N+ regions in the transistor-active region adjacent the recesses, deepening the recesses, diffusing boron into the deepened recesses to dope the substrate P-type beneath the N+ regions and also between the N+ regions, and patterning and metallizing the substrate to develop the electrical connections of the base, emitter and collector electrodes.
Inventors
- 👤 Sidney I. Soclof
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:11
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/184; H10P; H10P50/00; H10P50/20; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
75 words
The method of making a NPN lateral transistor on an N doped substrate, comprising the steps of: forming a recess in the substrate bounding the region for the transistor; N+ doping spaced apart portions of said regions; P doping the non-N+ doped portions of said region; filling said recess with field oxide; and, establishing electrical connections to each of said N+ spaced apart portions and to the P doped non-N+ doped portions of said region.
Claim 2
Independent Claim
75 words
The method of making a NPN lateral transistor on an N doped substrate, comprising the steps of: forming a recess in the substrate bounding the region for the transistor; N+ doping spaced apart portions of said regions; P doping the non-N+ doped portions of said region; filling said recess with field oxide; and, establishing electrical connections to each of said N+ spaced apart portions and to the P doped non-N+ doped portions of said region.
Claim 3
Independent Claim
153 words
A method for forming an array of sub-micron dimensioned NPN lateral transistors on a substrate doped N-type, wherein each transistor is formed comprising the following steps: masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary regions; doping of substrate via the slotted boundary regions to render regions of the substrate adjacent the boundary regions N+ doped; deepening the slotted boundary regions; doping the substrate via the deepened regions to render regions of the substrate beneath the N+ regions P doped; filling the deepened slotted boundary regions with field oxide; doping the active region of each transistor P type except for the N+ portions thereof; enhancing the last mentioned P type to P+ adjacent the substrate surface which is slotted; and, metallizing and patterning said substrate surface to provide electrical connections to each of said N+ regions and to said P+ region.
Claim 4
Independent Claim
153 words
A method for forming an array of sub-micron dimensioned NPN lateral transistors on a substrate doped N-type, wherein each transistor is formed comprising the following steps: masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary regions; doping of substrate via the slotted boundary regions to render regions of the substrate adjacent the boundary regions N+ doped; deepening the slotted boundary regions; doping the substrate via the deepened regions to render regions of the substrate beneath the N+ regions P doped; filling the deepened slotted boundary regions with field oxide; doping the active region of each transistor P type except for the N+ portions thereof; enhancing the last mentioned P type to P+ adjacent the substrate surface which is slotted; and, metallizing and patterning said substrate surface to provide electrical connections to each of said N+ regions and to said P+ region.
Claim 5
Dependent Claim
15 words
The method of claim 2, wherein; said slotting and deepening is effected by ion milling.
Claim 6
Dependent Claim
28 words
The method of claim 3, wherein; said N+ doping is achieved by diffusion following oxidation of the substrate and removal of the oxide from the slotted boundary regions.
Claim 7
Dependent Claim
14 words
The method of claim 4 wherein; said P doping is achieved by implanting boron.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |