Layout pattern for improved MOS device matching

Claim 1

A circuit layout, comprising: a number of metal oxide semiconductor field effect transistors each said transistor having a rectangular channel diffusion area bounded by a top edge, a bottom edge, an inside edge, and an outside edge wherein said transistors are arranged in a row so that said inside edge of each channel diffusion area is parallel to said inside edges of the remaining said channel diffusion areas, said outside edge of each channel diffusion area is parallel to said outside edges of the remaining said channel diffusion areas, said inside edge of each said channel diffusion area is parallel to said outside edge of each said channel diffusion area, said top edge of each said channel diffusion area is parallel to said bottom edge of each said channel diffusion area, said top edge of each said channel diffusion areas are perpendicular to said inside edge and said outside edge of each said channel diffusion area, said top edges of each said channel diffusion area lie on a single line, and said bottom edges of each said channel diffusion area lie on a single line; a number of gate electrodes equal to the number of said transistors wherein one of each said gate electrodes crosses each said channel diffusion area so that the edges of said gate electrodes are parallel to said top edge of said channel diffusion area; a source contact at each said channel diffusion area; a drain contact at each said channel diffusion area; a number of matched pairs of said transistors; and electrode connections to interconnect said transistors such that each said transistor forming one of said matched pairs has one of said transistors adjacent to said inside edge of said channel diffusion area of said transistor forming said matched pair and one of said transistors adjacent to said outside edge of said channel diffusion area of said transistor forming said matched pair.