High speed flat-cell mask ROM structure with select lines

Claim 1

A memory circuit on a semiconductor substrate, comprising: a flat cell ROM array including a plurality of sub-arrays, each sub-array including a plurality of first buried diffusion regions in the substrate, the regions forming odd and even diffusion lines in a section of the substrate; an insulating layer of substantially constant thickness over the section of the substrate; a plurality of block select transistors formed on the substrate; a plurality of conductive bit lines each coupled to a source of a different one of the block select transistors via a metal-to-diffusion region contact through the insulating layer; a plurality of word lines over the insulating layer and intersecting the first buried diffusion regions; a plurality of storage cells each including a storage cell field effect transistor having a channel in a region between a pair of the first buried diffusion regions and under one of the word lines, whereby a column of storage cells is formed between each pair of first buried diffusion regions and under the plurality of word lines; a plurality of second buried diffusion regions in the substrate, the plurality of second diffusion regions respectively corresponding to said even diffusion lines, wherein the plurality of second buried diffusion regions are respectively coupled, by means of a metal-to-diffusion region contact, to said conductive bit lines; a pair of conductive cell select lines over the insulating layer, the pair of conductive cell select lines intersecting the odd diffusion lines and said plurality of second buried diffusion regions, so that a region between each of said plurality of second buried diffusion regions and an adjacent one of said odd diffusion lines and under one of the conductive cell select lines, forms a channel of a cell select field effect transistor; and a conductive block select line over the insulating layer and coupled to a gate of each of the plurality of block select transistors, drains of said plurality of block select transistors being respectively coupled to said even diffusion lines, sources of said plurality of block select transistors being respectively coupled to a plurality of second diffusion regions of a preceding one of said plurality of sub-arrays.

Claim 7

The method of reading a cell of a sub-array block of a memory circuit, comprising: providing a flat-cell ROM array memory circuit; wherein the flat-cell ROM array memory circuit, comprises a flat cell ROM array including a plurality of sub-arrays, each sub-array including a plurality of first buried diffusion regions in a substrate, the regions forming odd and even diffusion lines in a section of the substrate; an insulating layer of substantially constant thickness over the section of the substrate; a plurality of block select transistors formed on the substrate; a plurality of conductive bit lines each coupled to a source of a different one of the block select transistors via a metal-to-diffusion region contact through the insulating layer; a plurality of word lines over the insulating layer and intersecting the first buried diffusion regions; a plurality of storage cells each including a storage cell field effect transistor having a channel in a region between a pair of the first buried diffusion regions and under one of the word lines, whereby a column of storage cells is formed between each pair of first buried diffusion regions and under the plurality of word lines; a plurality of second buried diffusion regions in the substrate, the plurality of second diffusion regions respectively corresponding to said even diffusion lines, wherein the plurality of second buried diffusion regions are respectively coupled, by means of a metal-to-diffusion region contact, to said conductive bit lines; a pair of conductive cell select lines over the insulating layer, the pair of conductive cell select lines intersecting the odd diffusion lines and said plurality of second buried diffusion regions, so that a region between each of said plurality of second buried diffusion regions and an adjacent one of said odd diffusion lines and under one of the conductive cell select lines, forms a channel of a cell select field effect transistor; wherein said pair of conductive cell select lines constitute a first and second cell select line, alternate ones of said plurality of storage cells being respectively associated with said first or second cell select line; and a conductive block select line over the insulating layer and coupled to a gate of each of the plurality of block select transistors, drains of said plurality of block select transistors being respectively coupled to said even diffusion lines, sources of said plurality of block select transistors being respectively coupled to a plurality of second diffusion regions of a preceding one of said plurality of sub-arrays; connecting said block select line to a first logic level; connecting a selected one of said plurality of word lines to the first logic level when a storage cell to be selected is connected to said selected word line and non-selected ones of said plurality of word lines being connected to a second logic level; and connecting first and second cell select transistors to the first and second logic levels, respectively, when the selected storage cell is associated with the first or second cell select line.

Claim 8

The method of reading a cell of a sub-array block of a memory circuit, comprising: providing a flat-cell ROM array memory circuit; wherein the flat-cell ROM array memory circuit, comprises a flat cell ROM array including a plurality of sub-arrays, each sub-array including a plurality of first buried diffusion regions in a substrate, the regions forming odd and even diffusion lines in a section of the substrate; an insulating layer of substantially constant thickness over the section of the substrate; a plurality of block select transistors formed on the substrate; a plurality of conductive bit lines each coupled to a source of a different one of the block select transistors via a metal-to-diffusion region contact through the insulating layer; a plurality of word lines over the insulating layer and intersecting the first buried diffusion regions; a plurality of storage cells each including a storage cell field effect transistor having a channel in a region between a pair of the first buried diffusion regions and under one of the word lines, whereby a column of storage cells is formed between each pair of first buried diffusion regions and under the plurality of word lines; a plurality of second buried diffusion regions in the substrate, the plurality of second diffusion regions respectively corresponding to said even diffusion lines, wherein the plurality of second buried diffusion regions are respectively coupled, by means of a metal-to-diffusion region contact, to said conductive bit lines; a pair of conductive cell select lines over the insulating layer, the pair of conductive cell select lines intersecting the odd diffusion lines and said plurality of second buried diffusion regions, so that a region between each of said plurality of second buried diffusion regions and an adjacent one of said odd diffusion lines and under one of the conductive cell select lines, forms a channel of a cell select field effect transistor; wherein said pair of conductive cell select lines constitute a first and second cell select line, alternate ones of said plurality of storage cells being respectively associated with said first or second cell select line; and a conductive block select line over the insulating layer and coupled to a gate of each of the plurality of block select transistors, drains of said plurality of block select transistors being respectively coupled to said even diffusion lines, sources of said plurality of block select transistors being respectively coupled to a plurality of second diffusion regions of a preceding one of said plurality of sub-arrays; connecting said block select line to a first logic level; connecting a selected one of said plurality of word lines to the first logic level when a storage cell to be selected is connected to said selected word line and non-selected ones of said plurality of word lines being connected to a second logic level; and connecting first and second cell select transistors to the first and second logic levels, respectively, when the selected storage cell is associated with the first or second cell select line.