US6168958B1
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US
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Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor
Assignee: Advanced Micro Devices Inc
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Filing: 1998-08-07
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Granted: 2001-01-02
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Expires: 2018-08-07
Abstract
Abstract A semiconductor structure having multiple thicknesses of high-k gate dielectrics and a process of manufacture. In one embodiment, semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate, the high permittivity layer having two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer. In another embodiment, a process for constructing a semiconductor structure includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.
Inventors
- 👤 Mark I. Gardner
- 👤 H. Jim Fulford
- 👤 Charles E. May
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:37
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10D84/8314; H10D84/83135
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
160 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer in a reaction chamber with a first etchant, including HBr and Cl 2 , wherein a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; purging the first etchant from the reaction chamber; introducing a second etchant, including CHF 3 and Argon, into the reaction chamber for etching the high permittivity layer; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; and forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness.
Claim 2
Dependent Claim
160 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer in a reaction chamber with a first etchant, including HBr and Cl 2 , wherein a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; purging the first etchant from the reaction chamber; introducing a second etchant, including CHF 3 and Argon, into the reaction chamber for etching the high permittivity layer; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; and forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness.
Claim 3
Dependent Claim
157 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer, whereby a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; forming a first set of spacers beside the first set of one or more gate electrodes before forming the second set of gate electrodes; and removing the first set of spacers after forming the second set of gate electrodes.
Claim 4
Dependent Claim
157 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer, whereby a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; forming a first set of spacers beside the first set of one or more gate electrodes before forming the second set of gate electrodes; and removing the first set of spacers after forming the second set of gate electrodes.
Claim 5
Dependent Claim
126 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness; forming a first set of one or more gate electrodes on the high permittivity layer having the first thickness; removing selected portions of the high permittivity layer, wherein the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; removing selected portions of the high permittivity layer, wherein the high permittivity layer is reduced to a third thickness; and forming a third set of gate electrodes on the selected portions of the high permittivity layer having the third thickness.
Claim 6
Dependent Claim
126 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness; forming a first set of one or more gate electrodes on the high permittivity layer having the first thickness; removing selected portions of the high permittivity layer, wherein the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; removing selected portions of the high permittivity layer, wherein the high permittivity layer is reduced to a third thickness; and forming a third set of gate electrodes on the selected portions of the high permittivity layer having the third thickness.
Claim 7
Dependent Claim
32 words
The structure of claim 3 wherein the high permittivity layer is comprised of material selected from the group of barium strontium titanate, tantalum oxide, lead zinc niobate, and lead scandium tantalum oxide.
Claim 8
Dependent Claim
21 words
The process of claim 3 , wherein one or more of the first set of gate electrodes are comprised of metal.
Claim 9
Dependent Claim
21 words
The process of claim 5 , wherein one or more of the second set of gate electrodes are comprised of polysilicon.
Claim 10
Dependent Claim
30 words
The process of claim 5 , wherein the metal of the one or more of the firs set of gate electrodes is selected from the group of tungsten and cobalt.
Claim 11
Dependent Claim
21 words
The process of claim 3 , wherein one or more of the first set of gate electrodes are comprised of polysilicon.
Claim 12
Dependent Claim
21 words
The process of claim 8 , wherein one or more of the second set of gate electrodes are comprised of metal.
Claim 13
Dependent Claim
157 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer, whereby a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; etching selected portions of the high permittivity layer to create a third thickness of the high permittivity layer; and forming a third set of gate electrodes on the selected portions of the high permittivity layer having the third thickness.
Claim 14
Dependent Claim
157 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer, whereby a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness; etching selected portions of the high permittivity layer to create a third thickness of the high permittivity layer; and forming a third set of gate electrodes on the selected portions of the high permittivity layer having the third thickness.
Claim 15
Dependent Claim
51 words
The process of claim 10 , further comprising: wherein etching the selected portions of the gate conductive layer is performed in a reaction chamber with a first etchant; purging the first etchant from the reaction chamber; and introducing a second etchant into the reaction chamber for etching the high permittivity layer.
Claim 16
Dependent Claim
36 words
The process of claim 11 , wherein the gate conductive layer is polysilicon and the first etchant is comprised of HBr and Cl 2 , and the second etchant is comprised of CHF 3 and Argon.
Claim 17
Dependent Claim
37 words
The process of claim 12 , further comprising implanting a first concentration of a first dopant species into the substrate adjacent the first set of one or more gate electrodes after removing the first set of spacers.
Claim 18
Dependent Claim
21 words
The process of claim 13 , wherein the first dopant species is selected from the group of boron, phosphorus, or arsenic.
Claim 19
Dependent Claim
25 words
The process of claim 14 , wherein the first concentration of the first dopant species is in the range of approximately 8e14-3e15 ions/cm 2 .
Claim 20
Dependent Claim
27 words
The process of claim 15 , wherein the first dopant species is implanted with an energy level in the range of approximately 0.5 KeV to 5 KeV.
Claim 21
Dependent Claim
29 words
The process of claim 13 , further comprising forming a second set of spacers beside the first set and second set of gate electrodes on the high permittivity layer.
Claim 22
Dependent Claim
26 words
The process of claim 17 , further comprising implanting a second concentration of a second dopant species into the substrate adjacent the second set of spacers.
Claim 23
Dependent Claim
21 words
The process of claim 18 , wherein the second dopant species is selected from the group of boron, phosphorus, or arsenic.
Claim 24
Dependent Claim
27 words
The process of claim 19 , wherein the second dopant species is implanted with an energy level in the range of approximately 0.2 KeV to 5 KeV.
Claim 25
Dependent Claim
24 words
The process of claim 20 , wherein the second dopant species is implanted with a dose rate of approximately 2E15-6 E15 ions/cm 2 .
Claim 26
Dependent Claim
25 words
The process of claim 10 , further comprising forming spacers beside the first set and second set of gate electrodes on the high permittivity layer.
Claim 27
Dependent Claim
79 words
The process of claim 10 , further comprising: implanting a first concentration of a first dopant species into the substrate beside the first set of gate electrodes after forming the first set of gate electrodes; forming a first set of spacers beside the first set of gate electrodes before forming the second set of gate electrodes; and implanting a second concentration of a second dopant species into the substrate adjacent the first set and second set of gate electrodes.
Claim 28
Dependent Claim
30 words
The process of claim 23 , further comprising forming a second set of spacers adjacent the second set of gate electrodes before implanting the second dopant species into the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |