US6167245A
Expired / Lapsed
US
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Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications
Assignee: Silicon Laboratories Inc
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Filing: 1998-05-29
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Granted: 2000-12-26
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Expires: 2018-05-29
Abstract
Abstract A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.
Inventors
- 👤 David R. Welland
- 👤 Caiyi Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/085; H03L7/16; H03L7/18; H03L7/183; H03L7/187; H03L7/197; H03L7/199; H03L7/22; H03L7/23; H03L7/087; H03L7/091
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
128 words
A method of operating a frequency synthesizer having a phase locked loop, comprising: generating at least one first clock signal, the first clock signal being derived from an output clock signal of phase locked loop; generating a second clock signal, the second clock signal being derived from a reference clock signal of phase locked loop; detecting a phase difference between the at least one first clock signal and the second clock signal; providing a phase difference output signal indicative of the detected phase difference; sampling and holding the phase difference output signal at timed intervals; generating at least one control signal from the sampling and holding step; and controlling the output frequency of a controllable oscillator of the phase locked loop with the at least one control signal.
Claim 2
Independent Claim
128 words
A method of operating a frequency synthesizer having a phase locked loop, comprising: generating at least one first clock signal, the first clock signal being derived from an output clock signal of phase locked loop; generating a second clock signal, the second clock signal being derived from a reference clock signal of phase locked loop; detecting a phase difference between the at least one first clock signal and the second clock signal; providing a phase difference output signal indicative of the detected phase difference; sampling and holding the phase difference output signal at timed intervals; generating at least one control signal from the sampling and holding step; and controlling the output frequency of a controllable oscillator of the phase locked loop with the at least one control signal.
Claim 3
Dependent Claim
138 words
The method of claim 1, the detecting a phase difference being performed with a phase detector having a plurality of first inputs, a second input, and at least a first output, the plurality of first inputs being coupled to an output of the controllable oscillator and the second input being coupled to the reference clock, the phase detector generating, a ramped analog output signal at the first output, the ramped analog output signal related to a phase difference between at least one of the first inputs and the second input; and the sampling and holding being performed with a sample and hold circuit coupled to the phase detector first output, the sample and hold circuit having at least one sample and hold output, the sample and hold output coupled to at least one input of the controllable oscillator.
Claim 4
Dependent Claim
25 words
The method of claim 2, wherein the plurality of first inputs are coupled to the controllable oscillator through a shift register and/or a clock divider.
Claim 5
Dependent Claim
27 words
The method of claim 2, the phase detector having a plurality of phase detector first outputs, the phase detector generating a plurality of ramped analog output signals.
Claim 6
Dependent Claim
33 words
The method of claim 4, wherein the sample and hold circuit has a plurality of outputs, and wherein the plurality of outputs are coupled to a plurality of inputs of the controllable oscillator.
Claim 7
Dependent Claim
33 words
The method of claim 2, wherein the sample and bold circuit has a plurality of outputs, and wherein the plurality of outputs are coupled to a plurality of inputs of the controllable oscillator.
Claim 8
Dependent Claim
14 words
The method of claim 6, wherein the controllable oscillator includes at least five inputs.
Claim 9
Dependent Claim
14 words
The method of claim 7, wherein the controllable oscillator includes at least twenty inputs.
Claim 10
Dependent Claim
28 words
The method of claim 2, further comprising a shift register coupled between the phase detector and the controllable oscillator output for generating one or more phase shifted signals.
Claim 11
Dependent Claim
21 words
The method of claim 2, the phase detector further comprising a ramped node, the ramped node being connected to a resistor.
Claim 12
Dependent Claim
38 words
The method of claim 1, the detecting a phase difference and providing a phase difference comprising: generating a ramped analog signal indicative of the difference between the at least one first clock signal and the second clock signal.
Claim 13
Dependent Claim
35 words
The method of claim 11, further comprising generating a plurality of control signals for controlling the output frequency of the controllable oscillator, at least one control signal being generated by sampling the ramped analog signal.
Claim 14
Dependent Claim
15 words
The method of claim 12, a further comprising generating a plurality of ramped analog signals.
Claim 15
Dependent Claim
23 words
The method of claim 13, further comprising sampling each of the plurality of ramped analog signals, to generate the plurality of control signals.
Claim 16
Dependent Claim
17 words
The method of claim 14, wherein the plurality of control signals includes at least five control signals.
Claim 17
Dependent Claim
25 words
The method of claim 11, the at least one first clock signal being a frequency divided and phase shifted version of the output clock signal.
Claim 18
Dependent Claim
47 words
The method of operating a frequency synthesizer of claim 1, further comprising the steps of generating a plurality of control signals from the sampling and holding step and controlling the output frequency of the controllable oscillator of the phase locked loop with the plurality of control signals.
Claim 19
Dependent Claim
23 words
The method of operating a frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least five signals.
Claim 20
Dependent Claim
23 words
The method of operating a frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least twenty signals.
Claim 21
Dependent Claim
41 words
The method of operating a frequency synthesizer of claim 1, further comprising the steps of generating a plurality of first clock signals and detecting a phase difference between each of the plurality of first clock signals and the second clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |