US4980653A
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Phase locked loop
Assignee: Motorola Solutions Inc
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Filing: 1989-09-05
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Granted: 1990-12-25
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Expires: 2009-09-05
Abstract
Abstract A phase locked loop (100) with a sample and hold phase detector (106) with adjustable gain. A switching circuit adjusts the slew rate of the phase detector by either introducing additional ramp capacitance (122) in the phase detector or by increasing the current for charging the ramp capacitor (116).
Inventors
- 👤 Wayne P. Shepherd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:22
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/08; H03L7/10; H03L7/107; H03L7/1077
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
114 words
A phase locked loop comprising: controlled oscillator means for providing an output signal, having a variable frequency responsive to a control signal; reference means for providing first and second reference signals; divider means for dividing the output signal by a predetermined divisor, to provide a divided signal; sample and hold phase detector means, having adjustable gain and slew rate, for comparing the phase of alternatively, the first and second reference signals with the phase of the divided signal; and: means for selectively adjusting the slew rate of the sample and hold phase detector means to optimize the adjustable gain of the phase detector means with respect to, alternatively, the first and second reference signals.
Claim 2
Dependent Claim
114 words
A phase locked loop comprising: controlled oscillator means for providing an output signal, having a variable frequency responsive to a control signal; reference means for providing first and second reference signals; divider means for dividing the output signal by a predetermined divisor, to provide a divided signal; sample and hold phase detector means, having adjustable gain and slew rate, for comparing the phase of alternatively, the first and second reference signals with the phase of the divided signal; and: means for selectively adjusting the slew rate of the sample and hold phase detector means to optimize the adjustable gain of the phase detector means with respect to, alternatively, the first and second reference signals.
Claim 3
Dependent Claim
48 words
The phase locked loop of claim 1, wherein the phase detector means has an adjustable slew rate, and the means for adjusting the gain of the phase detector means comprises a current source for applying a current signal to an adjustable capacitance means for determining the slew rate.
Claim 4
Dependent Claim
58 words
The phase locked loop of claim 1, wherein the phase detector means has an adjustable slew rate, and the means for adjusting the gain of the phase detector means comprises a variable current source coupled to the adjustable capacitance means for providing a variable current signal to the adjustable capacitance means, and for determining the the slew rate,
Claim 5
Dependent Claim
24 words
The phase locked loop of claim 1, further comprising an adaptive low-pass filter, disposed between the phase detector means and the controlled oscillator means.
Claim 6
Dependent Claim
16 words
The phase locked loop of claim 1, wherein the controlled oscillator means comprises a voltage-controlled oscillator.
Claim 7
Dependent Claim
13 words
The phase locked loop of claim 5, wherein the divider comprises a divider.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |