US5705955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency locked-loop using a microcontroller as a comparator
Assignee: Google Technology Holdings LLC
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Filing: 1995-12-21
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Granted: 1998-01-06
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Expires: 2015-12-21
Abstract
Abstract A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.
Inventors
- 👤 Thomas A. Freeburg
- 👤 John Ley
- 👤 Anne M. Pearce
- 👤 Gary Schulz
- 👤 Paul Odlyzko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:22
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
173 words
A frequency-locked loop comprising: a controllable oscillator for generating an output signal having a frequency the controllable oscillator having an input receiving a modulation signal in a transmission mode; a sampler, coupled to the controllable oscillator, for sampling the frequency of the output signal; a divider, coupled to the sampler, for dividing the frequency of the output signal to generate a prescaled signal; a microprocessor, coupled to the divider and the controllable oscillator, for performing a comparison of the prescaled signal to a reference signal and generating a non-continuous signal for correcting the frequency of the controllable oscillator output signal when not in the transmission mode, the microprocessor having instructions stored therein which control sampling by the sampler; a converter coupled to the microprocessor for converting the non-continuous control signal to an analog signal; a low pass filter coupled to the converter for filtering undesired components from the analog signal; and a summer coupled between the low pass filter and the controllable oscillator in order to provide for injection of the modulation signal.
Claim 2
Dependent Claim
173 words
A frequency-locked loop comprising: a controllable oscillator for generating an output signal having a frequency the controllable oscillator having an input receiving a modulation signal in a transmission mode; a sampler, coupled to the controllable oscillator, for sampling the frequency of the output signal; a divider, coupled to the sampler, for dividing the frequency of the output signal to generate a prescaled signal; a microprocessor, coupled to the divider and the controllable oscillator, for performing a comparison of the prescaled signal to a reference signal and generating a non-continuous signal for correcting the frequency of the controllable oscillator output signal when not in the transmission mode, the microprocessor having instructions stored therein which control sampling by the sampler; a converter coupled to the microprocessor for converting the non-continuous control signal to an analog signal; a low pass filter coupled to the converter for filtering undesired components from the analog signal; and a summer coupled between the low pass filter and the controllable oscillator in order to provide for injection of the modulation signal.
Claim 3
Dependent Claim
46 words
The frequency-locked loop of claim 1, wherein the converter is one of a group consisting of a digital-to-analog converter and a pulse width modulator, the low-pass filter and converter together being operable for converting non-continuous control signals to analog signals for delivery to the controllable oscillator.
Claim 4
Dependent Claim
40 words
The frequency-locked loop of claim 1 wherein power resources are removed from the divider when the microprocessor is not generating control signals for communication to the controllable oscillator while continuing to provide the reference signal from a reference signal source.
Claim 5
Dependent Claim
40 words
The frequency-locked loop of claim 1 wherein power resources are removed from the sampler when the microprocessor is not generating control signals for communication to the controllable oscillator while continuing to provide the reference signal from a reference signal source.
Claim 6
Independent Claim
109 words
A method for conserving power resources in a transmission circuit, comprising the steps of: generating an output signal having a variable frequency; performing, when in a non-transmission mode of operation, a comparison in a microprocessor of a prescaled signal, derived from the output signal, to a reference signal having a frequency, where the reference signal is a clock signal for the microprocessor; generating a non-continuous control signal for frequency adjusting the output signal based upon the comparison; operating in a transmission mode; and removing power resources from at least a portion of the transmission circuit when no control signal is being generated while continuing to provide the reference signal.
Claim 7
Independent Claim
109 words
A method for conserving power resources in a transmission circuit, comprising the steps of: generating an output signal having a variable frequency; performing, when in a non-transmission mode of operation, a comparison in a microprocessor of a prescaled signal, derived from the output signal, to a reference signal having a frequency, where the reference signal is a clock signal for the microprocessor; generating a non-continuous control signal for frequency adjusting the output signal based upon the comparison; operating in a transmission mode; and removing power resources from at least a portion of the transmission circuit when no control signal is being generated while continuing to provide the reference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-05 | 2001-07-07 | 2002-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-05 | 2005-07-07 | 2006-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-05 | 2009-07-07 | 2010-01-06 | $7700.00 | Window Closed / Lapsed |