US5369376A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable phase locked loop circuit and method of programming same
Assignee: Standard Microsystems LLC
•
Filing: 1991-11-29
•
Granted: 1994-11-29
•
Expires: 2011-11-29
Abstract
Abstract Programmable phase locked loop circuit and method of programming same. The cross-over frequency of the phase locked loop circuit can be changed solely by programming the gain constants of the phase-locked loop, while preserving the phase margin at each programmed operating frequency.
Inventors
- 👤 Hakan Leblebicioglu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:38
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898; H03L2207/00; H03L2207/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
331 words
A programmable phase locked loop circuit comprising: phase detection means being characterized by a phase error gain constant K p , and adapted for detecting the phase error between first and second input signals and generating as output a phase error signal representative of said phase error; a loop filter characterized by one or more phase margin contributing time constants T i and being operably associated with said phase detection means to receive as input said phase error signal and produce as output a control signal,each said phase margin contributing time constant T i being functionally dependent on an active element in said loop filter, and each said active element having a time constant contributing property functionally dependent on said phase error gain constant K p , and said phase error gain constant K p being proportional to a programmable current in said phase detection means, and said time constant contributing property of each said active element being functionally dependent on said programmable current; a variable frequency oscillator being characterized by an oscillator gain constant K o , and producing as output said second input signal having a frequency controlled by said control signal; said programmable phase locked loop circuit having, when programmed, a cross-over frequency, a phase margin at said cross-over frequency determined by said phase margin contributing time constants, and an open loop gain K m proportional to the product of said phase error gain constant K p and said oscillator gain constant; and programming means for programming the cross-over frequency of said programmable phase locked loop circuit and the phase margin thereof at said cross-over frequency, by adjusting said programmable current to one of a plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to one of said plurality of different cross-over frequencies while the phase margin of said programmable phase locked loop circuit is maintained substantially constant at each of said plurality of different cross-over frequencies.
Claim 2
Dependent Claim
331 words
A programmable phase locked loop circuit comprising: phase detection means being characterized by a phase error gain constant K p , and adapted for detecting the phase error between first and second input signals and generating as output a phase error signal representative of said phase error; a loop filter characterized by one or more phase margin contributing time constants T i and being operably associated with said phase detection means to receive as input said phase error signal and produce as output a control signal,each said phase margin contributing time constant T i being functionally dependent on an active element in said loop filter, and each said active element having a time constant contributing property functionally dependent on said phase error gain constant K p , and said phase error gain constant K p being proportional to a programmable current in said phase detection means, and said time constant contributing property of each said active element being functionally dependent on said programmable current; a variable frequency oscillator being characterized by an oscillator gain constant K o , and producing as output said second input signal having a frequency controlled by said control signal; said programmable phase locked loop circuit having, when programmed, a cross-over frequency, a phase margin at said cross-over frequency determined by said phase margin contributing time constants, and an open loop gain K m proportional to the product of said phase error gain constant K p and said oscillator gain constant; and programming means for programming the cross-over frequency of said programmable phase locked loop circuit and the phase margin thereof at said cross-over frequency, by adjusting said programmable current to one of a plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to one of said plurality of different cross-over frequencies while the phase margin of said programmable phase locked loop circuit is maintained substantially constant at each of said plurality of different cross-over frequencies.
Claim 3
Dependent Claim
48 words
The programmable phase locked loop circuit of claim 1, wherein said programming means increases said programmable current by a factor α, said phase error gain constant k p is increased by said factor α, and each said phase margin contributing time constant is decreased by said factor α.
Claim 4
Dependent Claim
54 words
The programmable phase locked loop circuit of claim 1, wherein said time constant contributing property of each said active element is electrical resistance, and said active element is physically realized in the form of a transistor biased in saturation, and wherein each said programmable current value is produced from an electronically controlled charge pump.
Claim 5
Independent Claim
428 words
A method of electronically programming a programmable phase locked loop circuit, comprising the steps: (a) providing a device employing a programmable phase locked loop circuit, said programmable phase locked loop circuit including (1) phase detection means being characterized by a phase error gain constant K p , and adapted for detecting the phase error between first and second input signals and generating as output a phase error signal representative of said phase error, (2) a loop filter characterized by one or more phase margin contributing time constants T i and being operably associated with said phase detection means to receive as input said phase error signal and produce as output a control signal,each said phase margin contributing time constant T i being functionally dependent on an active element in said loop filter, and each said active element having a time constant contributing property functionally dependent on said phase error gain constant K p , and said phase error gain constant K p being proportional to a programmable current in said phase detection means, and said time constant contributing property of each said active element being functionally dependent on said programmable current, (3) a variable frequency oscillator being characterized by an oscillator gain constant K o , and producing as output said second input signal having a frequency controlled by said control signal, (4) said programmable phase locked loop circuit having, when programmed, a cross-over frequency, a phase margin at said cross-over frequency determined by said phase margin contributing time constants, and an open loop gain K m proportional to the product of said phase error gain constant K p and said oscillator gain constant, and (5) programming means for programming the cross-over frequency of said programmable phase locked loop circuit and the phase margin thereof at said cross-over frequency, by setting said programmable current to one of a plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to one of said plurality of different cross-over frequencies while the phase margin of said programmable phase locked loop circuit is maintained substantially constant at each of said plurality of different cross-over frequencies; and (b) programming said cross-over frequency to a selected one of said plurality of different cross-over frequencies by solely setting said programmable current to one of said plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to said selected cross-over frequency while the phase margin of said programmable phase locked loop circuit is maintained substantially constant.
Claim 6
Independent Claim
428 words
A method of electronically programming a programmable phase locked loop circuit, comprising the steps: (a) providing a device employing a programmable phase locked loop circuit, said programmable phase locked loop circuit including (1) phase detection means being characterized by a phase error gain constant K p , and adapted for detecting the phase error between first and second input signals and generating as output a phase error signal representative of said phase error, (2) a loop filter characterized by one or more phase margin contributing time constants T i and being operably associated with said phase detection means to receive as input said phase error signal and produce as output a control signal,each said phase margin contributing time constant T i being functionally dependent on an active element in said loop filter, and each said active element having a time constant contributing property functionally dependent on said phase error gain constant K p , and said phase error gain constant K p being proportional to a programmable current in said phase detection means, and said time constant contributing property of each said active element being functionally dependent on said programmable current, (3) a variable frequency oscillator being characterized by an oscillator gain constant K o , and producing as output said second input signal having a frequency controlled by said control signal, (4) said programmable phase locked loop circuit having, when programmed, a cross-over frequency, a phase margin at said cross-over frequency determined by said phase margin contributing time constants, and an open loop gain K m proportional to the product of said phase error gain constant K p and said oscillator gain constant, and (5) programming means for programming the cross-over frequency of said programmable phase locked loop circuit and the phase margin thereof at said cross-over frequency, by setting said programmable current to one of a plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to one of said plurality of different cross-over frequencies while the phase margin of said programmable phase locked loop circuit is maintained substantially constant at each of said plurality of different cross-over frequencies; and (b) programming said cross-over frequency to a selected one of said plurality of different cross-over frequencies by solely setting said programmable current to one of said plurality of different programmable current values, whereby the cross-over frequency of said programmable phase locked loop circuit is automatically programmed to said selected cross-over frequency while the phase margin of said programmable phase locked loop circuit is maintained substantially constant.
Claim 7
Dependent Claim
57 words
The method of claim 4, where in step (a), said time constant contributing property of each said active element is electrical resistance, and each said active element is physically realized in the form of a transistor biased in saturation, and where in step (b) said selected programmable current value is produced from an electronically controlled charge pump.
References Cited (Backward Citations)
US4182994A
Cited
US4305045A
Cited
US4355413A
Cited
US4504800A
Cited
US4689581A
Cited
US4629999A
Cited
US4808884A
Cited
US4771249A
Cited
US4829258A
Cited
US4931749A
Cited
US5095288A
Cited
US5121085A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |