Stabilized phase locked loop

Claim 2

A circuit for providing a phase locked loop comprising: a multivibrator coupled to receive a trigger signal for triggering an output from said multivibrator; a phase comparator coupled to receive a reference signal having a predetermined pulse width and also coupled to receive said output from said multivibrator as a feedback signal for comparing said reference signal and said feedback signal; a filter coupled to said phase comparator for filtering said comparison of said reference and feedback signals and generating an error voltage wherein said error voltage is proportional to the amount of a phase difference of said comparison of said reference and feedback signals; a transconductance amplifier coupled to receiver said error voltage and coupled to provide an input current to said multivibrator, said input current being a function of said error voltage, wherein as said error voltage changes according to said comparison, said input current changes correspondingly to compensate for pulse width duration of said output signal such that said output signal will have an approximately equivalent pulse width duration as said reference signal.

Claim 3

The circuit of claim 1, wherein said transconductance amplifier includes a metering transistor wherein said error voltage is coupled to the gate of said transistor such that as said error voltage varies, conduction of said metering transistor varies correspondingly to vary said input current to said multivibrator.

Claim 4

The circuit of claim 2, wherein said multivibrator further includes an input charging capacitor such that said input current charges said capacitor to a predetermined level wherein said multivibrator changes states when said predetermined level is reached, said metering transistor and said input capacitor forming a RC time constant determining pulse width duration of said output signal.

Claim 5

The circuit of claim 3, wherein said filter has a single dominant pole in its transfer function.

Claim 6

The circuit of claim 4, wherein said multivibrator is a monostable multivibrator.

Claim 7

The circuit of claim 5, wherein said trigger signal and said reference signal are derived from a reference clock pulse.

Claim 8

The circuit of claim 6, wherein said circuit is embodied in a single integrated circuit ship.

Claim 9

A circuit for providing RC product stabilized phase locked loop comprising: (1) a secondary phase locked loop comprising: (a) a multivibrator coupled to receive a trigger signal for triggering a secondary output from said multivibrator; (b) a first phase comparator coupled to receive a first reference signal having a predetermined pulse width and also coupled to receive said secondary output from said multivibrator for comparing said first reference signal and said secondary output signal; (c) a first filter coupled to said first phase comparator for filtering said comparison of said first reference signal and said secondary output signal and generating an error voltage corresponding to said comparison; (d) a first transconductance amplifier coupled to said first filter and said multivibrator for receiving said error voltage signal from said first filter and for providing (1) a first input current to said multivibrator wherein said input current varies correspondingly to said error voltage for determining the pulse width duration of said secondary output from said multivibrator and (2) an analog trim information signal; (2) a primary phase locked loop, said primary phase locked loop comprising; (a) output means for providing a primary output and a feedback signal; (b) a second phase comparator coupled to receive an input signal having a selective frequency and also coupled to receive said feedback signal from said output means for comparing said input signal and said feedback signal; (c) a second filter coupled to said second phase comparator for filtering said comparison of said input signal and said feedback signal and generating a second error voltage responsive to said comparison; (d) a second transconductance amplifier, coupled to said second filter and said output means, for controlling a second input current to said output means, wherein said second input current varies correspondingly to said second error voltage such that as said second error voltage changes, said second input current changes accordingly to maintain lock of said primary loop; wherein said output means, said second phase comparator, said second filter, and said second transconductance amplifier are each coupled to receive said analog trim information signal from said first transconductance amplifier for centering an operating frequency of said output means, for controlling gain, and for providing compensation for said primary loop such that frequency of said primary loop is substantially independent of process and temperature variations, wherein compensation for said primary phase locked loop is provided by said secondary phase locked loop.

Claim 10

A circuit for providing RC product stabilized phase locked loop comprising: (1) a secondary phase locked loop comprising: (a) a multivibrator coupled to receive a trigger signal for triggering a secondary output from said multivibrator; (b) a first phase comparator coupled to receive a first reference signal having a predetermined pulse width and also coupled to receive said secondary output from said multivibrator for comparing said first reference signal and said secondary output signal; (c) a first filter coupled to said first phase comparator for filtering said comparison of said first reference signal and said secondary output signal and generating an error voltage corresponding to said comparison; (d) a first transconductance amplifier coupled to said first filter and said multivibrator for receiving said error voltage signal from said first filter and for providing (1) a first input current to said multivibrator wherein said input current varies correspondingly to said error voltage for determining the pulse width duration of said secondary output from said multivibrator and (2) an analog trim information signal; (2) a primary phase locked loop, said primary phase locked loop comprising; (a) output means for providing a primary output and a feedback signal; (b) a second phase comparator coupled to receive an input signal having a selective frequency and also coupled to receive said feedback signal from said output means for comparing said input signal and said feedback signal; (c) a second filter coupled to said second phase comparator for filtering said comparison of said input signal and said feedback signal and generating a second error voltage responsive to said comparison; (d) a second transconductance amplifier, coupled to said second filter and said output means, for controlling a second input current to said output means, wherein said second input current varies correspondingly to said second error voltage such that as said second error voltage changes, said second input current changes accordingly to maintain lock of said primary loop; wherein said output means, said second phase comparator, said second filter, and said second transconductance amplifier are each coupled to receive said analog trim information signal from said first transconductance amplifier for centering an operating frequency of said output means, for controlling gain, and for providing compensation for said primary loop such that frequency of said primary loop is substantially independent of process and temperature variations, wherein compensation for said primary phase locked loop is provided by said secondary phase locked loop.

Claim 11

The circuit of claim 8, wherein said second phase comparator functions as a charge pump.

Claim 12

The circuit of claim 9, wherein said output means includes a voltage controlled oscillator coupled to said second transconductance amplifier for controlling frequency of said primary phase locked loop.

Claim 13

The circuit of claim 10, wherein said output means further includes a frequency divider for dividing said primary output.

Claim 14

The circuit of claim 11, wherein said primary phase locked loop is used to provide data windows when data pulses are present on said input signal.

Claim 15

The circuit of claim 11, wherein said primary and secondary phase locked loops are fabricated on a same integrated circuit semiconductor chip.

Claim 16

The circuit of claim 8, wherein said RC product is proportional to said reference frequency and wherein said primary loop RC time constant is adjusted by said reference frequency.

Claim 17

The circuit of claim 12, wherein said RC product is proportional to said reference frequency and wherein said primary loop RC time constant is adjusted by said reference frequency.

Claim 18

The circuit of claim 1, wherein said multivibrator is a monostable multivibrator.

Claim 19

The circuit of claim 1, wherein said circuit is embodied in a single integrated circuit chip.