US4066978A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital phase-locked loop filter
Assignee: Charles Stark Draper Laboratory Inc
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Filing: 1977-01-24
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Granted: 1978-01-03
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Expires: 1997-01-24
Abstract
Abstract A phase processing system which includes at least one digital phase-locked loop wherein the phase of the input signal to the loop is compared with the phase of the loop output signal to produce a pulse-width modulated phase error signal. The error signal is digitally integrated, as by a counting means which cyclically counts the pulse widths thereof and provides a first control signal when the count reaches a first value and a second control signal when the count reaches a second value. The control signals are used to control the pulse rate of a clock signal to produce an intermediate clock signal such that when the first control signal is present a pulse is added thereto and when the second control signal is present a pulse is deleted therefrom. The intermediate clock signal is then fed to a feedback divider counting means which provides the loop output signal.
Inventors
- 👤 Duncan B. Cox, Jr.
- 👤 William H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:22
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03L7/0993; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
340 words
A phase processing system for filtering an input signal to produce a filtered output signal comprising a plurality of successively interconnected phase-locked loops, each of said loops including means responsive to first and second signals for producing a phase detected output signal representing the phase difference between said first and second signals; means responsive to said phase detected output signal and a first clock signal for digitally integrating said phase detected output signal to generate a first control signal whenever the value of said integrated signal reaches a first preselected level and to generate a second control signal whenever the value of said integrated signal reaches a second preselected level; means responsive to said first and second control signals and to a second clock signal for controllably changing the number of pulses from said second clock signal in accordance with the generation of said first or second control signal to produce an intermediate clock signal; means responsive to said intermediate clock signal of said pulse changing means signal for producing said second signal; the first signal of the first one of said successively connected loops being said input signal and the second signal of said first of said successively connected loops being said filtered output signal; the first signal of each of the remaining ones of said successively inter-connected loops being a signal selected from the pair of signals comprising the first signal and the second signal of the preceding loop; a reference clock means for producing a reference pulse clock signal having a fixed frequency; the first clock signal of each of said loops having a preselected frequency determined by the frequency of said reference pulse clock signal; the second clock signal of the last of said successively connected plurality of loops having a preselected frequency determined by the frequency of said reference pulse clock signal and the intermediate clock signal of each of said loops except the first one of said loops being connected as the second clock signal of the pulse changing means in each preceding loop.
Claim 2
Dependent Claim
340 words
A phase processing system for filtering an input signal to produce a filtered output signal comprising a plurality of successively interconnected phase-locked loops, each of said loops including means responsive to first and second signals for producing a phase detected output signal representing the phase difference between said first and second signals; means responsive to said phase detected output signal and a first clock signal for digitally integrating said phase detected output signal to generate a first control signal whenever the value of said integrated signal reaches a first preselected level and to generate a second control signal whenever the value of said integrated signal reaches a second preselected level; means responsive to said first and second control signals and to a second clock signal for controllably changing the number of pulses from said second clock signal in accordance with the generation of said first or second control signal to produce an intermediate clock signal; means responsive to said intermediate clock signal of said pulse changing means signal for producing said second signal; the first signal of the first one of said successively connected loops being said input signal and the second signal of said first of said successively connected loops being said filtered output signal; the first signal of each of the remaining ones of said successively inter-connected loops being a signal selected from the pair of signals comprising the first signal and the second signal of the preceding loop; a reference clock means for producing a reference pulse clock signal having a fixed frequency; the first clock signal of each of said loops having a preselected frequency determined by the frequency of said reference pulse clock signal; the second clock signal of the last of said successively connected plurality of loops having a preselected frequency determined by the frequency of said reference pulse clock signal and the intermediate clock signal of each of said loops except the first one of said loops being connected as the second clock signal of the pulse changing means in each preceding loop.
Claim 3
Dependent Claim
32 words
A phase processing system in accordance with claim 1 wherein the first signal of each of said remaining ones of said successively inter-connected loops is the first signal of the preceding loop.
Claim 4
Dependent Claim
32 words
A phase processing system in accordance with claim 1 wherein the first signal of each of said remaining ones of said successively inter-connected loops is the second signal of the preceding loop.
Claim 5
Dependent Claim
59 words
A phase processing system in accordance with claim 1 wherein the first signal of a first number of said remaining ones of said successively interconnected loops is the first signal of the preceding loop and the first signal of a second number of said remaining ones of said successively interconnected loops is the second signal of the preceding loop.
Claim 6
Dependent Claim
95 words
A phase processing system in accordance with claim 1, said system comprising a pair of loops for providing a second-order filtering system wherein the second signal of the first of said pair of loops is said filtered output signal; the first signal of the second of said pair of loops being a signal selected from the pair of signals comprising the first and second signals of said first loop, and the intermediate clock signal of said second of said pair of loops is the second clock signal of the first of said pair of loops.
Claim 7
Dependent Claim
31 words
A phase processing system in accordance with claim 5 wherein the second signal of the said pair of loops is the first signal of the second of said pair of loops.
Claim 8
Dependent Claim
33 words
A phase processing system in accordance with claim 5 wherein the first signal of the first of said pair of loops is the first signal of the second of said pair of loops.
Claim 9
Dependent Claim
60 words
A phase processing system in accordance with claim 7 wherein said second signal producing means of said first loop changes the pulse rate of the intermediate clock signal thereof by factor N 1 ; said second signal producing means of said second loop changes the pulse rate of the intermediate clock signal thereof by a different factor N 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-02 | 1981-07-04 | 1982-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-02 | 1985-07-04 | 1986-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-02 | 1989-07-04 | 1990-01-03 | $7700.00 | Window Closed / Lapsed |