EP0249060A2
Expired / Lapsed
EP
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Self-adjusting single-shot for phase-locked oscillator
Assignee: International Business Machines Corp
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Filing: 1987-05-19
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Granted: —
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Expires: 2007-05-19
Abstract
Abstract A VCO-based circuit (100) locks the width of a generated pulse to the width of a clock pulse, even though the latter pulse occurs at a different time than the former. The circuit has a VCO (123), a latch (130) for input data pulses, pulse-delay means (150), and a pulse generator (140) whose width is controlled by a logical combination of signals from its own output, the VCO, and the delayed data pulses.
Inventors
- 👤 James Wilson Rae;
- 👤 David Peter Swart
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:59
CPC Classifications
H; H03; H03L; H03L7/00; H03K; H03K3/00; H03K3/01; H03K3/017; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
131 words
A circuit for tracking a source of input pulses occurring in a sequence of windows, characterized in that it comprises: a controlled oscillator (123) for producing clock pulses defining said windows in response to control pulses and data pulses; a data latch (130) responsive to said input pulses and to said clock pulses for producing said data pulses; delay means (150) for shifting said data pulses to a later time; a pulse generator (140) for producing said control pulses having a duration related to the duration of said clock pulses, said pulse generator including control means (143) responsive to said delay means, said clock pulses and to said control pulses for producing a correction signal, a single-shot (141) for producing said control pulses having a width responsive to said correction signal.
Claim 2
Dependent Claim
131 words
A circuit for tracking a source of input pulses occurring in a sequence of windows, characterized in that it comprises: a controlled oscillator (123) for producing clock pulses defining said windows in response to control pulses and data pulses; a data latch (130) responsive to said input pulses and to said clock pulses for producing said data pulses; delay means (150) for shifting said data pulses to a later time; a pulse generator (140) for producing said control pulses having a duration related to the duration of said clock pulses, said pulse generator including control means (143) responsive to said delay means, said clock pulses and to said control pulses for producing a correction signal, a single-shot (141) for producing said control pulses having a width responsive to said correction signal.
Claim 3
Dependent Claim
33 words
A circuit according to Claim 1, characterized in that the time constant for appreciable change in the width of said control pulse is very large compared to the width of said control pulse.
Claim 4
Dependent Claim
35 words
A circuit according to Claim 1 or 2, characterized in that said control means is responsive to said control pulses to decrease the width of said correction pulses with increasing width of said control pulses.
Claim 5
Dependent Claim
35 words
A circuit according to Claim 3, characterized in that said control means includes logic responsive to a predetermined combination of said clock pulses and said data pulses to increase the width of said correction pulses.
Claim 6
Dependent Claim
38 words
A circuit according to anyone of Claims 1-4, characterized in that said delay means delays the beginning of said data pulses to one of said windows following that one of said windows in which it had originally begun.
Claim 7
Dependent Claim
28 words
A circuit according to Claim 5, characterized in that said delay means is further adapted to standardize the width of all said data pulses to a single value.
Claim 8
Dependent Claim
57 words
A circuit according to anyone of Claims 1-6, characterized in that said controlled oscillator is adapted to increase the frequency of said clock pulses for a first combination of said data pulses and said control pulses, and to decrease the frequency of said clock pulses for a second combination of said data pulses and said clock pulses.
Claim 9
Dependent Claim
49 words
A circuit according to Claim 7, characterized in that one of said first and second combinations occurs when said data pulses are on while said control pulses are off, and wherein the other of said combinations occurs when said data pulses are off while said control pulses are on.
Claim 10
Independent Claim
109 words
A method for locking the width of a control pulse to the width of a reference clock pulse for a wave cycle in which said control pulse need have no transition simultaneous with a transition of said clock pulse, characterized in that it comprises: generating a sequence of said clock pulses; initiating a data pulse and said control pulse in response to an input pulse; generating a first correction signal tending to decrease the width of said control pulse from said control pulse itself; generating a second correction signal tending to increase the width of said control pulse from a function of said clock pulse and said data pulse.
Claim 11
Independent Claim
109 words
A method for locking the width of a control pulse to the width of a reference clock pulse for a wave cycle in which said control pulse need have no transition simultaneous with a transition of said clock pulse, characterized in that it comprises: generating a sequence of said clock pulses; initiating a data pulse and said control pulse in response to an input pulse; generating a first correction signal tending to decrease the width of said control pulse from said control pulse itself; generating a second correction signal tending to increase the width of said control pulse from a function of said clock pulse and said data pulse.
Claim 12
Dependent Claim
24 words
A method according to Claim 9, characterized in that said function of said clock pulse and said data pulse includes delaying said data pulse.
References Cited (Backward Citations)
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