US4771249A
Expired / Lapsed
US
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Phase locked loop having a filter with controlled variable bandwidth
Assignee: NXP USA Inc
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Filing: 1987-05-26
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Granted: 1988-09-13
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Expires: 2007-05-26
Abstract
Abstract A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.
Inventors
- 👤 Kenneth R. Burch
- 👤 Wendell L. Little
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:51
CPC Classifications
H; H03; H03L; H03L3/00; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/107; H03L7/1075; H03L7/16; H03L7/18; H03L7/085; H03L7/089; H03L7/0891; H03L7/0893; H03L7/0895; H03L7/0898
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
236 words
A phase locked loop circuit for providing an output signal which is locked to a predetermined frequency, comprising: input means having a first input for receiving a reference frequency and a second input for receiving a fundamental frequency of the output signal, said input means comparing the phase of the reference and fundamental frequencies and providing first and second phase signals indicating the phase of each frequency with respect to the other frequency; filter means having a bandwidth and coupled to the input means for receiving the first and second phase signals and filtering the reference frequency to provide a control signal, said control signal having an amplitude proportional to the first and second phase signals; oscillator means having an input coupled to the filter means for receiving the control signal, and an output for providing the output signal in response to the control signal; frequency divider means coupled to the output of the oscillator means, for receiving the output signal and dividing the output signal by a predetermined multiple to provide the fundamental frequency; and control means coupled to the filter means for controlling the bandwidth of the filter means by setting the bandwidth at a first value in response to the first and second phase signals and setting the bandwidth at a second value in response to detecting the output signal resepectively exceeding and dropping below the predetermined frequency a predetermined number of times.
Claim 2
Dependent Claim
236 words
A phase locked loop circuit for providing an output signal which is locked to a predetermined frequency, comprising: input means having a first input for receiving a reference frequency and a second input for receiving a fundamental frequency of the output signal, said input means comparing the phase of the reference and fundamental frequencies and providing first and second phase signals indicating the phase of each frequency with respect to the other frequency; filter means having a bandwidth and coupled to the input means for receiving the first and second phase signals and filtering the reference frequency to provide a control signal, said control signal having an amplitude proportional to the first and second phase signals; oscillator means having an input coupled to the filter means for receiving the control signal, and an output for providing the output signal in response to the control signal; frequency divider means coupled to the output of the oscillator means, for receiving the output signal and dividing the output signal by a predetermined multiple to provide the fundamental frequency; and control means coupled to the filter means for controlling the bandwidth of the filter means by setting the bandwidth at a first value in response to the first and second phase signals and setting the bandwidth at a second value in response to detecting the output signal resepectively exceeding and dropping below the predetermined frequency a predetermined number of times.
Claim 3
Dependent Claim
61 words
The phase locked loop of claim 1 wherein the control means further comprise: detection means coupled to the filter means for detecting when one of the reference frequency or the fundamental frequency has a greater magnitude; and counter means coupled to the detection means, for counting a predetermined number of times the output signal exceeds and drops below the predetermined frequency.
Claim 4
Dependent Claim
18 words
The phase locked loop of claim 2 wherein the predetermined number counted by the counter means is three.
Claim 5
Dependent Claim
28 words
The phase locked loop of claim 1 wherein the first value of the bandwidth set by the control means is substantially larger in magnitude than the second value.
Claim 6
Independent Claim
175 words
A method for controlling bandwidth in a filter of a phase locked loop to improve speed and stability, comprising the steps of: receiving an input reference frequency; filtering the input reference frequency to provide a control voltage; coupling the control voltage to an oscillator circuit to provide an output signal which is phase locked to the input reference frequency, said output signal having a frequency varying in proportion to the control signal; dividing the output signal by an integer multiple to provide a feedback frequency having a fundamental frequency of the output signal; comparing the phase of the input reference frequency with the phase of the feedback frequency; placing the filter in a first predetermined bandwidth in response to the compared phase being greater than a predetermined ratio; detecting when the output signal exceeds and falls below a predetermined frequency a predetermined number of times; and placing the filter in a second predetermined bandwidth in response to the detection of the output signal exceeding and falling below the predetermined frequency the predetermined number of times.
Claim 7
Independent Claim
175 words
A method for controlling bandwidth in a filter of a phase locked loop to improve speed and stability, comprising the steps of: receiving an input reference frequency; filtering the input reference frequency to provide a control voltage; coupling the control voltage to an oscillator circuit to provide an output signal which is phase locked to the input reference frequency, said output signal having a frequency varying in proportion to the control signal; dividing the output signal by an integer multiple to provide a feedback frequency having a fundamental frequency of the output signal; comparing the phase of the input reference frequency with the phase of the feedback frequency; placing the filter in a first predetermined bandwidth in response to the compared phase being greater than a predetermined ratio; detecting when the output signal exceeds and falls below a predetermined frequency a predetermined number of times; and placing the filter in a second predetermined bandwidth in response to the detection of the output signal exceeding and falling below the predetermined frequency the predetermined number of times.
Claim 8
Dependent Claim
25 words
The method of claim 5 wherein the predetermined number of times to detect the output signal exceeding and falling below the predetermined frequency is three.
Claim 9
Dependent Claim
240 words
A phase locked loop circuit having a filter with controlled variable bandwidth, comprising: phase detection means having a first input for receiving a reference frequency and a second input for receiving a feedback signal, said phase detection means comparing the phase of the reference and feedback signals and providing first and second phase signals indicating the phase of each frequency with respect to the other frequency; filter means coupled to the phase detection means, said filter means filtering the reference frequency to provide a control signal having an amplitude proportional to the first and second phase signals; oscillator means having an input coupled to the filter means for receiving the control signal, and an output for providing an output signal of predetermined frequency phase locked to the reference frequency and in response to the control signal; frequency divider means coupled to the output of the oscillator means, for receiving the output signal and dividing the output signal by a predetermined multiple to provide the feedback signal; and control means coupled to the filter means for varying the bandwidth of the filter means between a wide bandwidth mode and a narrow bandwidth mode, said wide bandwidth mode being used whenever the reference frequency and the feedback frequency differ in frequency by more than a predetermined amount and said narrow bandwidth mode being used after the output signal has exceeded and fallen below a predetermined output frequency a predetermined number of times.
Claim 10
Dependent Claim
240 words
A phase locked loop circuit having a filter with controlled variable bandwidth, comprising: phase detection means having a first input for receiving a reference frequency and a second input for receiving a feedback signal, said phase detection means comparing the phase of the reference and feedback signals and providing first and second phase signals indicating the phase of each frequency with respect to the other frequency; filter means coupled to the phase detection means, said filter means filtering the reference frequency to provide a control signal having an amplitude proportional to the first and second phase signals; oscillator means having an input coupled to the filter means for receiving the control signal, and an output for providing an output signal of predetermined frequency phase locked to the reference frequency and in response to the control signal; frequency divider means coupled to the output of the oscillator means, for receiving the output signal and dividing the output signal by a predetermined multiple to provide the feedback signal; and control means coupled to the filter means for varying the bandwidth of the filter means between a wide bandwidth mode and a narrow bandwidth mode, said wide bandwidth mode being used whenever the reference frequency and the feedback frequency differ in frequency by more than a predetermined amount and said narrow bandwidth mode being used after the output signal has exceeded and fallen below a predetermined output frequency a predetermined number of times.
Claim 11
Dependent Claim
33 words
The phase locked loop circuit of claim 7 wherein said wide bandwidth mode is used when the reference frequency and the feedback frequency differ by at least a factor of two or more.
Claim 12
Dependent Claim
28 words
The phase locked loop circuit of claim 7 wherein the narrow bandwidth mode is used after the output signal exceeds and falls below the output frequency three times.
References Cited (Backward Citations)
US4156855A
Cited
US4506233A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |