Bandwidth control circuit for a phase locked loop

Claim 2

A control circuit for a phase locked loop having a reference oscillator, a controlled oscillator, a phase detector having inputs coupled to said oscillators, and a filter coupled between an output of said phase detector and a control input of said controlled oscillator, said control circuit comprising: a. an input circuit having an output that produces a high voltage and an output that produces a low voltage, relative to each other, each being proportional to the voltage at said phase detector output; b. first and second comparator circuits each having first and second inputs and an output; c. means coupling said first input of said first comparator circuit to said low voltage output of said input circuit; d. means coupling said second input of said second comparator circuit to said high voltage output of said input circuit; e. a first delay circuit coupling said second input of said first comparator circuit to said high voltage output of said input circuit; f. a second delay circuit coupling said first input of said second comparator circuit to said low voltage output of said input circuit; g. and output means coupled to said outputs of both of said first and second comparator circuits for producing a control signal for application of said filter.

Claim 3

The control circuit of claim 1 wherein said output means include a comparator circuit having a first input coupled to said outputs of said first and second comparator circuits, and having a second input coupled to a reference voltage.

Claim 4

The control circuit of claim 1 or claim 2 wherein each of said delay circuits comprise a capacitor charging circuit.

Claim 5

A phase locked loop control circuit comprising: a. a voltage divider circuit for coupling to a phase detector output and for providing a relatively high voltage proportional to said phase detector output and for providing a relatively low voltage proportional to said phase detector output; b. first and second comparator circuits each having first and second inputs and an output, said output having a first magnitude in response to said first input exceeding said second input and having a second magnitude in response to said second input exceeding said first input; c. means coupling said low voltage output of said voltage divider circuit to said first input of said first comparator circuit; d. means coupling said high voltage output of said voltage divider circuit to said second input of said second comparator circuit; e. a first time delay circuit coupling said second input of said first comparator circuit to said high voltage output of said voltage divider circuit; f. a second time delay circuit coupling said first input of said second comparator circuit to said low voltage output of said voltage divider circuit; g. and means combining said outputs of said first and second comparator circuits for controlling a filter circuit in said phase locked loop circuit.

Claim 6

A phase locked loop control circuit comprising: a. a voltage divider circuit for coupling to a phase detector output and for providing a relatively high voltage proportional to said phase detector output and for providing a relatively low voltage proportional to said phase detector output; b. first and second comparator circuits each having first and second inputs and an output, said output having a first magnitude in response to said first input exceeding said second input and having a second magnitude in response to said second input exceeding said first input; c. means coupling said low voltage output of said voltage divider circuit to said first input of said first comparator circuit; d. means coupling said high voltage output of said voltage divider circuit to said second input of said second comparator circuit; e. a first time delay circuit coupling said second input of said first comparator circuit to said high voltage output of said voltage divider circuit; f. a second time delay circuit coupling said first input of said second comparator circuit to said low voltage output of said voltage divider circuit; g. and means combining said outputs of said first and second comparator circuits for controlling a filter circuit in said phase locked loop circuit.

Claim 7

The control circuit of claim 4 wherein said comparator circuits comprise operational amplifiers.

Claim 8

The control circuit of claim 4 or claim 5 wherein said combining means comprise a threshold circuit that produces an output in response to either of said comparator circuit outputs exceeding a selected magnitude.

Claim 9

The control circuit of claim 4 or claim 5 wherein said time delay circuits introduce a time delay to changes in said high voltage output of said voltage divider circuit, said time delay being a function of the amount of said changes in signal level.

Claim 10

The control circuit of claim 6 wherein said time delay circuits introduce a time delay to changes in said high voltage output of said voltage divider circuit, said time delay being a function of the amount of said changes in signal level.