US6165815A
Expired / Lapsed
US
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Method of fabrication of stacked semiconductor devices
Assignee: Round Rock Research LLC
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Filing: 1997-04-18
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Granted: 2000-12-26
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Expires: 2017-04-18
Abstract
Abstract A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be die into individual die pairs or wafer portions containing more than one dice pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe. The die pair face opposite the substrate attachment side (opposing side) and may have a plurality of bond pads. Bond wires or TAB leads are attached between bond pads on the opposing side and corresponding conductive trace or lead ends on the substrate. Alternately, both the attachment side and opposing side may have an array of minute solder balls or small pins for respective attachment to two facing substrates on opposite sides of the die pair.
Inventors
- 👤 Michael B. Ball
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:56
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7402; H10D; H10D62/00; H10D62/10; H10D62/117; H10W; H10W90/00; H10P72/7416; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/07339; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W74/00; H10W74/10; H10W74/15; H10W90/20; H10W90/231; H10W90/24; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/752; H10W90/754
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
194 words
A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising: providing a first semiconductor substrate wafer having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate wafer having a first side including a plurality of integrated circuits thereon and having a backside; and stacking said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer in at least partially superimposed relationship having the back side of the first semiconductor substrate wafer facing the back side of the at least one second semiconductor substrate wafer; aligning vertically said first semiconductor substrate wafer and the at least one second semiconductor substrate wafer, thereby vertically aligning integrated circuitry on the first semiconductor substrate wafer and at least one of the plurality of integrated circuits on said at least one semiconductor substrate wafer; and severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate wafer and an aligned die including at least one of said plurality of integrated circuits from said at least one second semiconductor substrate wafer.
Claim 2
Independent Claim
194 words
A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising: providing a first semiconductor substrate wafer having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate wafer having a first side including a plurality of integrated circuits thereon and having a backside; and stacking said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer in at least partially superimposed relationship having the back side of the first semiconductor substrate wafer facing the back side of the at least one second semiconductor substrate wafer; aligning vertically said first semiconductor substrate wafer and the at least one second semiconductor substrate wafer, thereby vertically aligning integrated circuitry on the first semiconductor substrate wafer and at least one of the plurality of integrated circuits on said at least one semiconductor substrate wafer; and severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate wafer and an aligned die including at least one of said plurality of integrated circuits from said at least one second semiconductor substrate wafer.
Claim 3
Dependent Claim
23 words
The method of claim 1, further including adhesively attaching said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer.
Claim 4
Dependent Claim
12 words
The method of claim 2, wherein said adhesive comprises a dicelectric adhesive.
Claim 5
Dependent Claim
27 words
The method of claim 1, further including disposing a heat sink element between said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer.
Claim 6
Dependent Claim
87 words
The method of claim 1, wherein said first semiconductor substrate wafer and at least one second semiconductor substrate wafer each include locations defining discrete dice or wafer portions severable from said first semiconductor substrate wafer and at least one second semiconductor substrate wafer, and the locations of said dice or wafer portions on said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer are vertically alignable when said first semiconductor substrate wafer and at least one second semiconductor substrate wafer are vertically superimposed.
Claim 7
Dependent Claim
52 words
The method of claim 1, wherein said first semiconductor substrate wafer and the at least one second semiconductor substrate wafer each include a flat, and said vertical alignment is effected by aligning said flat of said first semiconductor substrate wafer and said flat of the at least one second semiconductor substrate wafer.
Claim 8
Dependent Claim
25 words
The method of claim 1, further comprising directly electrically connecting a first die of said at least one dice pair to conductors of a substrate.
Claim 9
Dependent Claim
29 words
The method of claim 7, wherein said direct electrical connection is selected from a group comprising reflowable metal elements, polymer elements having a conductive capability, and preformed lead-type elements.
Claim 10
Dependent Claim
24 words
The method of claim 7, further comprising directly electrically connecting both dice of said at least one dice pair to conductors of a substrate.
Claim 11
Dependent Claim
28 words
The method of claim 7, further comprising electrically connecting a second die of said at least one dice pair to conductors of a substrate through intermediate connection elements.
Claim 12
Dependent Claim
24 words
The method of claim 10, wherein said intermediate connection elements are selected from a group consisting of bond wires and traces of flex circuits.
Claim 13
Dependent Claim
29 words
The method of claim 1, further comprising electrically connecting said at least one dice pair to conductors of a substrate and encapsulating said at least one dice pair thereafter.
Claim 14
Independent Claim
308 words
A method of fabricating a multi-level stack of semiconductor wafer segments, each of said semiconductor wafer segments including integrated circuitry, comprising: providing a first semiconductor substrate wafer having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate wafer having a first side including a plurality of integrated circuits thereon and having a back side; stacking said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer in at least partially superimposed relationship to form a stack of semiconductor wafer substrates; separating said stack thereby forming at least two semiconductor wafer segment stacks, each said semiconductor wafer segment stack comprising a first semiconductor wafer segment having a side including integrated circuitry and a back side and at least one other semiconductor wafer segment having a side including integrated circuitry and a back side, stacking said at least two semiconductor wafer segment stacks in at least partially superimposed relationship; locating bond pads on said first semiconductor wafer segment of at least one of said at least two semiconductor wafer segment stacks on the side adjacent said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks at a periphery thereof; and forming a notch through said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks to provide access to at least one said peripheral bond pad of said first semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks.
Claim 15
Independent Claim
308 words
A method of fabricating a multi-level stack of semiconductor wafer segments, each of said semiconductor wafer segments including integrated circuitry, comprising: providing a first semiconductor substrate wafer having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate wafer having a first side including a plurality of integrated circuits thereon and having a back side; stacking said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer in at least partially superimposed relationship to form a stack of semiconductor wafer substrates; separating said stack thereby forming at least two semiconductor wafer segment stacks, each said semiconductor wafer segment stack comprising a first semiconductor wafer segment having a side including integrated circuitry and a back side and at least one other semiconductor wafer segment having a side including integrated circuitry and a back side, stacking said at least two semiconductor wafer segment stacks in at least partially superimposed relationship; locating bond pads on said first semiconductor wafer segment of at least one of said at least two semiconductor wafer segment stacks on the side adjacent said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks at a periphery thereof; and forming a notch through said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks to provide access to at least one said peripheral bond pad of said first semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks.
Claim 16
Dependent Claim
109 words
The method of claim 13, further including stacking said first semiconductor wafer segments of said at least one of said at least two semiconductor wafer segment stack with the integrated circuitry side of said first semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks proximate the back side of said at least one other semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks, and locating said bond pads on said integrated circuitry side of said first semiconductor wafer segment of said at least one of said at least two semiconductor wafer segment stacks.
Claim 17
Dependent Claim
34 words
The method of claim 13, further including adhesively attaching said first and said at least one other semiconductor wafer segments of said at least one of said at least two semiconductor wafer segment stacks.
Claim 18
Dependent Claim
66 words
The method of claim 15, wherein said adhesively attaching said first and said at least one other semiconductor wafer segments of said at least one of said at least two semiconductor wafer segment stacks comprises adhesively attaching said first and said at least one other semiconductor wafer segments of said at least one of said at least two semiconductor wafer segment stacks with a dielectric adhesive.
Claim 19
Dependent Claim
24 words
The method of claim 13, further including disposing a heat sink element between said first and said at least one other semiconductor wafer segments.
Claim 20
Dependent Claim
30 words
The method of claim 13, further comprising directly electrically connecting at least one of said first and said at least one other semiconductor wafer segment to conductors of a substrate.
Claim 21
Dependent Claim
28 words
The method of claim 18, wherein said direct electrical connection is achieved with a connection element selected from a group comprising bond wires and traces of flex circuits.
Claim 22
Independent Claim
154 words
A method of fabricating a multi-level stack of semiconductor wafers, each of said semiconductor wafers including integrated circuitry, comprising: providing a first semiconductor wafer having a first side including integrated circuitry and having a back side; providing at least one other semiconductor wafer having a first side including integrated circuitry and having a back side; stacking said first semiconductor wafer and said at least one other semiconductor wafer in at least partially superimposed relationship; locating bond pads on said first semiconductor wafer of said stack on the side proximate said at least one other semiconductor wafer at a periphery thereof; and forming a notch through said at least one other semiconductor wafer, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer to provide access to at least one said peripheral bond pads of said first semiconductor wafer of said stack.
Claim 23
Independent Claim
154 words
A method of fabricating a multi-level stack of semiconductor wafers, each of said semiconductor wafers including integrated circuitry, comprising: providing a first semiconductor wafer having a first side including integrated circuitry and having a back side; providing at least one other semiconductor wafer having a first side including integrated circuitry and having a back side; stacking said first semiconductor wafer and said at least one other semiconductor wafer in at least partially superimposed relationship; locating bond pads on said first semiconductor wafer of said stack on the side proximate said at least one other semiconductor wafer at a periphery thereof; and forming a notch through said at least one other semiconductor wafer, said notch extending between and substantially perpendicular to a circuitry side and a back side of said at least one other semiconductor wafer to provide access to at least one said peripheral bond pads of said first semiconductor wafer of said stack.
Claim 24
Dependent Claim
45 words
The method of claim 20, further including stacking said first semiconductor wafer and said at least one second semiconductor wafer with a third semiconductor wafer, having the integrated circuitry side of said first semiconductor wafer segment proximate the back side of said third semiconductor wafer.
Claim 25
Dependent Claim
21 words
The method of claim 20, further including adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer.
Claim 26
Dependent Claim
40 words
The method of claim 22, wherein said adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer comprises adhesively attaching said first semiconductor wafer and said at least one other semiconductor wafer with a dielectric adhesive.
Claim 27
Dependent Claim
25 words
The method of claim 20, further including disposing a heat sink element between said first semiconductor wafer and said at least one other semiconductor wafer.
Claim 28
Dependent Claim
28 words
The method of claim 20, further comprising directly electrically connecting at least one of said first semiconductor wafer and said other semiconductor wafer to conductors of a substrate.
Claim 29
Dependent Claim
28 words
The method of claim 25, wherein said direct electrical connection is achieved with a connection element selected from a group comprising bond wires and traces of flex circuits.
Claim 30
Dependent Claim
60 words
The method of claim 20, wherein said first semiconductor wafer and said at least one other semiconductor wafer are stacked with the integrated circuit side of said first semiconductor wafer facing the back side of said at least one other semiconductor wafer, and wherein said peripheral bond pads are located on the integrated circuit side of said first semiconductor wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |