US6163066A
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Porous silicon dioxide insulator
Assignee: Round Rock Research LLC
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Filing: 1998-08-24
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Granted: 2000-12-19
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Expires: 2018-08-24
Abstract
Abstract A porous silicon dioxide insulator having a low relative dielectric constant of about 2.0 or less is formed from a silicon carbide base layer. Initially, at least one layer of silicon carbide is deposited on a semiconductor substrate. The silicon carbide layer is then etched to form a porous silicon carbide layer, which is oxidized to produce the final porous silicon dioxide layer.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:41
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/6903; H10P14/6905; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6529; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072; H10W20/40; H10W20/45; H10W20/46; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10P14/66; H10P14/665; H10P14/692; H10P14/6921; H10P14/6922; Y; Y10; Y10S; Y10S438/00; Y10S438/96
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
62 words
A memory cell array comprising digit lines, word lines, active areas and memory cells, the array further comprising a porous silicon dioxide insulating layer between the digit lines, word lines, active areas, and memory cells, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer.
Claim 2
Dependent Claim
62 words
A memory cell array comprising digit lines, word lines, active areas and memory cells, the array further comprising a porous silicon dioxide insulating layer between the digit lines, word lines, active areas, and memory cells, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer.
Claim 3
Dependent Claim
25 words
The memory cell array of claim 1, wherein the porous silicon dioxide insulator layer has an effective relative dielectric constant of about 2.0 or less.
Claim 4
Dependent Claim
23 words
The memory cell array of claim 1, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 5
Dependent Claim
29 words
The memory cell array of claim 1, wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array.
Claim 6
Dependent Claim
29 words
The memory cell array of claim 1, wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect.
Claim 7
Dependent Claim
32 words
The memory cell array of claim 1, wherein at least a portion of the digit lines or word lines in direct contact with the porous silicon dioxide insulating layer comprises a metal.
Claim 8
Dependent Claim
13 words
The memory cell array of claim 4, wherein the interconnect structure comprises metal.
Claim 9
Dependent Claim
77 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array.
Claim 10
Dependent Claim
77 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array.
Claim 11
Dependent Claim
25 words
The memory cell array of claim 8, wherein the porous silicon dioxide insulator layer has an effective relative dielectric constant of about 2.0 or less.
Claim 12
Dependent Claim
77 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect.
Claim 13
Dependent Claim
77 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect.
Claim 14
Dependent Claim
25 words
The memory cell array of claim 10, wherein the porous silicon dioxide insulator layer has an effective relative dielectric constant of about 2.0 or less.
Claim 15
Dependent Claim
70 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 16
Dependent Claim
70 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 17
Dependent Claim
24 words
The memory cell array of claim 12, wherein the porous silicon dioxide insulator layer has an effective dielectric constant of about 2.0 or less.
Claim 18
Dependent Claim
29 words
The memory cell array of claim 12, wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array.
Claim 19
Dependent Claim
29 words
The memory cell array of claim 12, wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect.
Claim 20
Dependent Claim
97 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of the interconnect structure.
Claim 21
Dependent Claim
97 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of the interconnect structure.
Claim 22
Dependent Claim
23 words
The memory cell array of claim 16, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 23
Dependent Claim
24 words
The memory cell array of claim 16, wherein the porous silicon dioxide insulator layer has an effective dielectric constant of about 2.0 or less.
Claim 24
Dependent Claim
104 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of at least one of the first and second metallization layers.
Claim 25
Dependent Claim
104 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, and wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of at least one of the first and second metallization layers.
Claim 26
Dependent Claim
23 words
The memory cell array of claim 19, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 27
Dependent Claim
29 words
The memory cell array of claim 19, wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array.
Claim 28
Dependent Claim
24 words
The memory cell array of claim 19, wherein the porous silicon dioxide insulator layer has an effective dielectric constant of about 2.0 or less.
Claim 29
Dependent Claim
103 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of the interconnect structure, and wherein the interconnect structure comprises metal.
Claim 30
Dependent Claim
103 words
A memory cell array having digit lines and word lines, the array comprising a porous silicon dioxide insulating layer between adjacent digit lines and adjacent word lines, wherein at least one of the digit lines or at least one of the word lines is in direct contact with the porous silicon dioxide insulating layer, wherein the porous silicon dioxide insulator is interposed between an access transistor gate and an interconnect structure in the memory cell array, wherein the porous silicon dioxide insulating layer is in direct contact with at least a portion of the interconnect structure, and wherein the interconnect structure comprises metal.
Claim 31
Dependent Claim
23 words
The memory cell array of claim 23, wherein the porous silicon dioxide insulator layer has a porosity of about 30% to about 60%.
Claim 32
Dependent Claim
29 words
The memory cell array of claim 23, wherein the porous silicon dioxide insulator is interposed between a first metallization layer and a second metallization layer in a multilevel interconnect.
Claim 33
Dependent Claim
24 words
The memory cell array of claim 23, wherein the porous silicon dioxide insulator layer has an effective dielectric constant of about 2.0 or less.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-19 | 2004-06-19 | 2004-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-19 | 2008-06-19 | 2008-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-19 | 2012-06-19 | 2012-12-19 | $7700.00 | Window Closed / Lapsed |