Patent US6161208A successfully refreshed from Google Patents.
US6161208A
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Storage subsystem including an error correcting cache and means for performing memory to memory transfers
Assignee: International Business Machines Corp
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Filing: 1999-04-14
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Granted: 2000-12-12
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Expires: 2019-04-14
Abstract
Abstract A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.
Inventors
- 👤 Patrick Francis Dutton
- 👤 Steven Lee Gregor
- 👤 Hehching Harry Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897; G06F2211/00; G06F2211/10; G06F2211/1002; G06F2211/109
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
130 words
A method for detecting and correcting an error in data in a cache location due to a hardware failure in said cache location, said data having a parity bit, said method comprising the steps of: detecting a parity error in said data in said cache location; writing said data to an outpage buffer; inverting said data from said outpage buffer and writing the inverted data to an inpage buffer; writing said inverted data from said inpage buffer to said cache location; reading said inverted data from said cache location; and after said reading, inverting said inverted data to yield corrected data, and writing said corrected data into said outpage buffer, whereby said corrected data in said outpage buffer is corrected for a single bit hardware failure in said cache location.
Claim 2
Independent Claim
130 words
A method for detecting and correcting an error in data in a cache location due to a hardware failure in said cache location, said data having a parity bit, said method comprising the steps of: detecting a parity error in said data in said cache location; writing said data to an outpage buffer; inverting said data from said outpage buffer and writing the inverted data to an inpage buffer; writing said inverted data from said inpage buffer to said cache location; reading said inverted data from said cache location; and after said reading, inverting said inverted data to yield corrected data, and writing said corrected data into said outpage buffer, whereby said corrected data in said outpage buffer is corrected for a single bit hardware failure in said cache location.
Claim 3
Dependent Claim
25 words
A system according to claim 1 wherein a parity checker detects said error in said data and is disabled during all the subsequent recited steps.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-12 | 2004-06-12 | 2004-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-12 | 2008-06-12 | 2008-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-12 | 2012-06-12 | 2012-12-12 | $7700.00 | Window Closed / Lapsed |