US5428632A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit for dual port memory
Assignee: STMicroelectronics lnc USA
•
Filing: 1991-04-30
•
Granted: 1995-06-27
•
Expires: 2011-04-30
Abstract
Abstract A memory device provides a control circuit attached to a parity bit position of a memory array. When a selected single bit within an array entry has its value changed without affecting the remaining bits of the entry, the control circuit senses the previous value of the parity bit and internally stores the complement of that value into the parity bit position for that entry. This complementing of the parity bit occurs during the same memory cycle in which the selected bit is changed. Complementing of the parity bit to ensure proper parity function occurs without communication off of the device, and so is completely transparent to the outside world.
Inventors
- 👤 Bahador Rastegar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:16
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
166 words
A control circuit for a dual port cache tag random access memory having a plurality of entries, each entry having a parity bit and a single selected bit, wherein a first port can change only the parity bit and the selected bit for an entry, comprising: a detector for indicating that the single bit in an addressed memory entry is changed; a sensor for sensing a state of the parity bit for such an addressed entry; and a controller connected to said sensor and to said detector for, in response to a single bit in an addressed entry being changed, changing the state of the parity bit for such an entry; wherein said controller writes a value into the parity bit for an addressed entry during every system write cycle, wherein the value so written is unchanged from its previous value if a cache miss occurred on the first port, and is complemented from its previous value if a cache hit occurred on the first port.
Claim 2
Dependent Claim
166 words
A control circuit for a dual port cache tag random access memory having a plurality of entries, each entry having a parity bit and a single selected bit, wherein a first port can change only the parity bit and the selected bit for an entry, comprising: a detector for indicating that the single bit in an addressed memory entry is changed; a sensor for sensing a state of the parity bit for such an addressed entry; and a controller connected to said sensor and to said detector for, in response to a single bit in an addressed entry being changed, changing the state of the parity bit for such an entry; wherein said controller writes a value into the parity bit for an addressed entry during every system write cycle, wherein the value so written is unchanged from its previous value if a cache miss occurred on the first port, and is complemented from its previous value if a cache hit occurred on the first port.
Claim 3
Dependent Claim
26 words
The control circuit of claim 1, wherein only one preselected bit of an entry can be changed without writing a new value to the entire entry.
Claim 4
Dependent Claim
49 words
The control circuit of claim 1, wherein the bit changeable by the first port has a value of 1 to indicate a valid entry, and is set to a value of 0 when a system address on the first port matches an array entry during a system write cycle.
Claim 5
Dependent Claim
22 words
The control circuit of claim 1, wherein a second port to the memory can write a new value to an entire entry.
Claim 6
Dependent Claim
70 words
The control circuit of claim 1, wherein said controller comprises: means for latching a value detected by said sensor; a logic circuit responsive to said detector for providing the latched value when the selected bit is not changed, and for providing the complement for the latched value when the selected bit is changed; and a write buffer for writing the provided value into the parity bit of the addressed entry.
Claim 7
Dependent Claim
31 words
The control circuit of claim 5, wherein said write buffer is enabled to write the provided value only during a write cycle for a bus memory attached to the first port.
Claim 8
Dependent Claim
31 words
The control circuit of claim 6, further comprising: a delay means connected to said write buffer for delaying an enabling input thereto until the end of a system bus write cycle.
Claim 9
Independent Claim
90 words
A method for retaining valid parity in a dual port memory device having first and second ports, and having a plurality of entries in an array and the capability for changing only the value of a single bit and a parity bit within a single selected entry of the array from the second port, comprising the steps of: detecting the occurrence of a change of the single bit in an array entry by the second port; when such a change is detected, complementing the parity bit for such array entry.
Claim 10
Independent Claim
90 words
A method for retaining valid parity in a dual port memory device having first and second ports, and having a plurality of entries in an array and the capability for changing only the value of a single bit and a parity bit within a single selected entry of the array from the second port, comprising the steps of: detecting the occurrence of a change of the single bit in an array entry by the second port; when such a change is detected, complementing the parity bit for such array entry.
Claim 11
Dependent Claim
68 words
The method of claim 8, wherein said detecting step comprises the steps of: determining the occurrence of a match between an array entry and a value on a system bus; and determining the occurrence of a system bus write cycle; wherein the single bit is changed by the second port, and is detected to occur, in response to a match being determined to occur during a write cycle.
Claim 12
Dependent Claim
20 words
The method of claim 9, wherein said complementing step is performed at the end of a system bus write cycle.
Claim 13
Dependent Claim
38 words
The method of claim 9, further comprising the step of: when a system write cycle occurs but there is no match with an array entry, writing the uncomplemented value of the parity bit back into the array entry.
Claim 14
Dependent Claim
163 words
A memory device, comprising: a dual port memory array having a plurality of entries, each entry including a first bit and a parity bit; a first port interface connected to the memory array for addressing the entries, and reading data from and writing data into addressed array entries; a second port connected to the memory array for addressing the entries, and for, in response to a detected condition, writing a selected value into the first bit of an addressed entry; a detector for indicating that the first bit in the entry addressed by the second port has been changed by the second port; a sensor for sensing a state of the parity bit for the entry for which the first bit has been changed by the second port; and a controller connected to the sensor and the detector for, in response to the detector indicating that the first bit has been changed, changing the state of the parity bit for such an entry.
Claim 15
Dependent Claim
163 words
A memory device, comprising: a dual port memory array having a plurality of entries, each entry including a first bit and a parity bit; a first port interface connected to the memory array for addressing the entries, and reading data from and writing data into addressed array entries; a second port connected to the memory array for addressing the entries, and for, in response to a detected condition, writing a selected value into the first bit of an addressed entry; a detector for indicating that the first bit in the entry addressed by the second port has been changed by the second port; a sensor for sensing a state of the parity bit for the entry for which the first bit has been changed by the second port; and a controller connected to the sensor and the detector for, in response to the detector indicating that the first bit has been changed, changing the state of the parity bit for such an entry.
Claim 16
Dependent Claim
35 words
The memory device of claim 12, wherein the detected condition is a match between a data entry addressed by the second port and an address on a computer system bus during a system write cycle.
Claim 17
Dependent Claim
70 words
The memory device of claim 12, wherein said controller comprises: means for latching a value detected by the sensor; a logic circuit responsive to the detector for providing the latched value when the first bit is not changed, and for providing the complement for the latched value when the first bit is changed; and a write buffer for writing the provided value into the parity bit of the addressed entry.
Claim 18
Dependent Claim
31 words
The memory device of claim 14, wherein the write buffer is enabled to write the provided value only during a write cycle for a bus memory attached to the first port.
Claim 19
Dependent Claim
31 words
The memory device of claim 6, further comprising: a delay means connected to the write buffer for delaying an enabling input thereto until the end of a system bus write cycle.
Claim 20
Dependent Claim
25 words
The memory device of claim 12, wherein the second port is capable of changing only the first bit and the parity bit for any entry.
Claim 21
Dependent Claim
14 words
The memory device of claim 17, wherein the memory is a cache tag memory.
Claim 22
Dependent Claim
45 words
The memory device of claim 18, wherein the first bit has a value of 1 to indicate a valid entry, and is set to a value of 0 when a system address on the second port matches an array entry during a system write cycle.
Claim 23
Dependent Claim
65 words
The memory device of claim 19, wherein the controller writes a value into the parity bit for an entry addressed by the second port during every system write cycle, wherein the value so written is unchanged from its previous value if a cache miss occurred on the second port, and is complemented from its previous value if a cache hit occurred on the second port.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |