Mechanism for lock-up free cache operation with a remote address translation unit

Claim 2

A virtual addressable cache memory organization for use with a central processing unit generating load requests and an address translation unit for translating a system virtual address to a real memory address comprising: (a) a virtual addressable cache memory; (b) cache hit determination means responsive to a load request for determining the hit or miss condition of access to a cache memory address; (c) address determination means for determining the cache memory address of an available location in said cache memory upon determination of a cache miss condition by said cache hit determination means; (d) as least one miss information holding register for storing the system virtual address of a load request and the cache memory address of an available location in said cache memory determined by said address determination means in response to said cache hit determination means determining a cache miss; (e) first indicator means responsive to at least one miss information holding register for indicating that the miss information holding register stores information; and (f) second indicator means responsive to said address translation unit being unable to translate the system virtual address in respect of the load request for which said miss information holding register was allocated for indicating that the previously allocated miss information holding register is de-allocated.

Claim 3

The virtual addressable cache memory organization of claim 1 further comprising: (g) means responsive to a miss information holding register storing a cache memory address of an available location in said cache memory for storing the system virtual address stored in the miss information holding register in said virtual addressable cache memory at a location in said cache memory determined by the cache memory address of an available location in cache memory stored in said miss information holding register; and (h) internal purge means responsive to said address translation unit being unable to translate the system virtual address stored at said location in said cache memory for indicating that data stored at said location in said cache memory is invalid.

Claim 4

The virtual addressable cache memory organization of claim 2 further comprising: (i) means responsive to the operation of said internal purge means to bypass said cache memory.

Claim 5

The virtual addressable cache memory organization of claim 1 further comprising: (g) means responsive to a miss information holding register storing a cache memory address of an available location in said cache memory for storing the system virtual address stored in the miss information holding register and a valid indicator in said virtual addressable cache memory at a location in said cache memory addressed by the cache address of an available location in cache memory stored in said miss information holding register; and (h) internal purge means responsive to said address translation unit being unable to translate the system virtual address stored at said location in said cache memory for clearing said valid indicator.

Claim 6

The virtual addressable cache memory organization of claim 4 further comprising: (i) means responsive to the operation of said internal a purge means to by pass said cache memory.

Claim 7

The virtual addressable cache memory organization of claim 1 wherein said virtual addressable cache memory comprises a tag directory, a used and least recently used status memory and a data memory and further comprising: (g) means responsive to the storage of a cache memory address of an available location in a miss information holding register for storing the system virtual address stored in the miss information holding register to said tag directory and for storing a valid indicator in said used and least recently used status memory at a location in said tag directory and in said used and least recently used memory addressed by the cache memory address of an available location in cache memory stored in said misinformation holding register; (h) third indicator means responsive to said address translation unit indicating it is unable to translate the system virtual address stored in a miss information holding register for indicating that said cache memory organization is unavailable to service further request; (i) fourth indicator means responsive to said address translation unit indicating it is unable to translate the system virtual address stored in a miss information holding register for indicating the miss information holding register; (j) means responsive to said cache determination means determination of a cache miss for clearing the valid indicator at the available location in said cache memory stored in a miss information holding register indicated by said fourth indicator means; (k) means responsive to clearing said valid indicator for clearing said fourth indicator means; (l) means responsive to clearing all said fourth indicator means for clearing said third indicator means.

Claim 8

The virtual addressable cache memory organization of claim 6 wherein said means for storing a valid indicator to said used and least recently used status memory include registers associated with said at least one miss information holding register for storing the cache memory address of an available location stored in said at least one miss information holding register upon determination of a cache miss by said cache hit determination means in respect of a load request.

Claim 9

The virtual addressable cache memory organization of claim 6 further comprising: (m) means responsive to said fourth indicator means to bypass said cache memory.

Claim 10

The virtual addressable cache memory organization of claim 1 wherein said second indicator means includes a counter incremented each time said address translation unit is unable to translate an address in processing a load request.

Claim 11

The virtual addressable cache memory organization of claim 9 wherein said cache memory is arranged in cache lines containing words and said counter provides an overflow signal after being incremented as many times as there are words in a cache line, said overflow signal initiating de-allocation of the respective miss information holding register.