US4370710A
Expired / Lapsed
US
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Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
Assignee: LAURENCE J MARHOEFER
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Filing: 1980-08-26
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Granted: 1983-01-25
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Expires: 2000-08-26
Abstract
Abstract A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory has a faster rate of operation than the rate of operation of central memory. The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device. The miss information holding register section allows for an almost continual stream of new requests for data to be supplied to the cache memory at the cache hit rate throughput.
Inventors
- 👤 David Kroft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859; G06F12/0888
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
334 words
A cache memory organization comprised of; a cache memory unit, selection unit means for selecting the input to said cache memory unit, a tag arrays and control unit means connected to and for providing a first data input for forming a first address input to said selection unit means, input stack means connected to and for providing a second data input to said selection unit means, a miss information holding registers unit connected to and for providing a third data input for forming a second address input to said selection unit means, wherein said miss information holding registers unit receives an input from said tag arrays and control unit means, wherein said miss information holding registers unit holds a predetermined number of required addresses not found in said cache memory unit when said cache memory unit is addressed and misses, a miss information comparator and status collection network connected to said miss information registers holding unit and receiving input request and cache memory addresses from said tag arrays and control unit means and for providing status information to said tag arrays and control unit means, a memory receiver unit for receiving data from a central memory of a computer system, said memory receiver unit being connected to said input stack means and to said miss information holding registers unit for providing addresses to said input stack means under control of said miss information holding registers unit, an output selection network for the cache memory organization having a first input from the cache memory unit, a second input from said input stack means and a third input from said memory receiver unit wherein said cache memory organization is not locked up when said cache memory unit is addressed and misses by means of said miss information holding registers unit holding miss addresses until said memory receiver unit receives the required miss address information while said tag arrays and control unit means continues to provide addresses to said cache memory unit through said selection unit means.
Claim 2
Dependent Claim
334 words
A cache memory organization comprised of; a cache memory unit, selection unit means for selecting the input to said cache memory unit, a tag arrays and control unit means connected to and for providing a first data input for forming a first address input to said selection unit means, input stack means connected to and for providing a second data input to said selection unit means, a miss information holding registers unit connected to and for providing a third data input for forming a second address input to said selection unit means, wherein said miss information holding registers unit receives an input from said tag arrays and control unit means, wherein said miss information holding registers unit holds a predetermined number of required addresses not found in said cache memory unit when said cache memory unit is addressed and misses, a miss information comparator and status collection network connected to said miss information registers holding unit and receiving input request and cache memory addresses from said tag arrays and control unit means and for providing status information to said tag arrays and control unit means, a memory receiver unit for receiving data from a central memory of a computer system, said memory receiver unit being connected to said input stack means and to said miss information holding registers unit for providing addresses to said input stack means under control of said miss information holding registers unit, an output selection network for the cache memory organization having a first input from the cache memory unit, a second input from said input stack means and a third input from said memory receiver unit wherein said cache memory organization is not locked up when said cache memory unit is addressed and misses by means of said miss information holding registers unit holding miss addresses until said memory receiver unit receives the required miss address information while said tag arrays and control unit means continues to provide addresses to said cache memory unit through said selection unit means.
Claim 3
Dependent Claim
60 words
The cache memory organization of claim 1 in which said miss information holding register unit consists of a predetermined number of registers of each of the following types: a cache memory address register, an input request address register, an identification tags register, a send-to-CPU indicators register, a partial write code register, an in-input-stack indicators register, and a control information register.
Claim 4
Dependent Claim
19 words
The cache memory organization of claim 2 in which the predetermined number of each of said registers is 4.
Claim 5
Dependent Claim
121 words
The cache memory organization of claim 1 in which the miss information comparator has a predetermined number of ways of comparison and is comprised of: a predetermined number of selectors to send status information to the tag array control unit, a predetermined number of selectors to send the cache memory address and partial write code to select unit, a predetermined number of selectors to send control, selected identification tag and send to CPU indicator information to the memory receiver, network means for forming the logical product and logical sum for the totally written out and partially written status registers, and a hit resolve network to determine from the compare outputs the single and multiple hit status for the tag array control.
Claim 6
Dependent Claim
19 words
The cache memory organization of claim 4 in which the predetermined number for each of said means is 4.
Claim 7
Dependent Claim
175 words
The cache memory organization of claim 1 in which said miss information holding register unit consists of a predetermined number of registers of each of the following types: a cache memory address register, an input request address register, an identification tags register, a send-to-CPU indicators register, a partial write code register, an in-input-stack indicators register, and a control information register and in which the miss information comparator has a predetermined number of ways of comparison and is comprised of: a predetermined number of selectors to send status information to the tag array control unit, a predetermined number of selectors to send the cache memory address and partial write code to select unit, a predetermined number of selectors to send control, selected identification tag and send to CPU indicator information to the memory receiver, network means for forming the logical product and logical sum for the totally written out and partially written status registers, and a hit resolve network to determine from the compare outputs the single and multiple hit status for the tag array control.
Claim 8
Dependent Claim
19 words
The cache memory organization of claim 6 in which the predetermined number for each of said means is 4.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-24 | 1986-07-26 | 1987-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-24 | 1990-07-26 | 1991-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-24 | 1994-07-26 | 1995-01-25 | $7700.00 | Window Closed / Lapsed |