Data processing system having a high speed buffer memory

Claim 1

In a data processing system having: a main memory for storing data which includes instruction words and operands; a buffer memory, coupled to said main memory, for storing, by way of data transfer from said main memory, part of the data stored in said main memory; an instruction control unit, coupled to said buffer memory, for decoding instruction words read out of said buffer memory and for obtaining operand addresses; and an arithmetic unit, coupled to said instruction control unit and said buffer memory, for processing instruction words decoded by said instruction control unit in response to operands read out from said buffer memory in accordance with operand addresses from said instruction control unit; the improvement comprising: first means, including said instruction control unit, for detecting that an instruction word read out from said buffer memory corresponds to a prescribed type of instruction in accordance with which said arithmetic unit successively utilizes a sequence of operands which are stored in successive regions of said main memory; and second means, coupled to said main memory, said buffer memory, said instruction control unit, and said first means, for successively causing each operand in said sequence of operands to be transferred from said main memory to said buffer memory in accordance with an operand address from said instruction control unit, in response to said first means detecting said prescribed type of instruction.