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US4056845A
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Memory access technique
Assignee: EMC Corp
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Filing: 1975-04-25
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Granted: 1977-11-01
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Expires: 1995-04-25
Abstract
Abstract A memory access technique for use in digital data processing apparatus, particularly in mini-computer systems, in which a plurality of memory modules are used, each of the modules having a main memory and a higher speed auxiliary, or "cache" memory, the data in the "cache" memories of a plurality of modules being capable of storage therein in an interleaved manner. Appropriate modifiable interconnection means, such as modifiable jumper connections, are provided on each memory module to permit the modules to be arranged for either interleaved or non-interleaved operation. As additional modules are added to the system, additional "cache" memory storage is automatically added and the capability of higher order interleaving becomes readily possible.
Inventors
- 👤 William P. Churchill, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0851
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
194 words
A memory module for use in a data processing system having a plurality of memory modules and a memory address bus for transferring addresses in said system, each said memory module comprising a main memory means operable at a first speed; an auxiliary memory means operable at a second speed higher than said first speed for temporarily storing selected portions of the data stored in said main memory means; associative memory means for temporarily storing selected main memory addresses and comparing the stored addresses with an address supplied from said memory address bus to said associative memory means during a read or write operation to generate comparison data for indicating whether data requested by said supplied address is stored in said auxiliary memory means; and means for storing said selected data portions in said auxiliary memory means so that the data stored in the auxiliary memory means of all of said plurality of memory modules are arranged in an interleaved manner such that data which are expected to be referenced sequentially during the operation of said data processing system are sequentially stored in the auxiliary memory means of different ones of said memory modules.
Claim 2
Dependent Claim
194 words
A memory module for use in a data processing system having a plurality of memory modules and a memory address bus for transferring addresses in said system, each said memory module comprising a main memory means operable at a first speed; an auxiliary memory means operable at a second speed higher than said first speed for temporarily storing selected portions of the data stored in said main memory means; associative memory means for temporarily storing selected main memory addresses and comparing the stored addresses with an address supplied from said memory address bus to said associative memory means during a read or write operation to generate comparison data for indicating whether data requested by said supplied address is stored in said auxiliary memory means; and means for storing said selected data portions in said auxiliary memory means so that the data stored in the auxiliary memory means of all of said plurality of memory modules are arranged in an interleaved manner such that data which are expected to be referenced sequentially during the operation of said data processing system are sequentially stored in the auxiliary memory means of different ones of said memory modules.
Claim 3
Dependent Claim
61 words
A memory module for use in a data processing system in accordance with claim 1 wherein said system comprises N memory modules, where N is an even integer, said selected data portions being stored in an N-way interleaving manner such that each sequential group of N sequential words is stored sequentially in the auxiliary memory means of said N memory modules.
Claim 4
Dependent Claim
19 words
A memory module for use in a data processing system in accordance with claim 2 where N is 8.
Claim 5
Dependent Claim
19 words
A memory module for use in a data processing system in accordance with claim 2 wherein N is 4.
Claim 6
Dependent Claim
19 words
A memory module for use in a data processing system in accordance with claim 2 wherein N is 2.
Claim 7
Dependent Claim
76 words
A memory module for use in a data processing system in accordance with claim 1 wherein the addresses used in said system are arranged to include a first plurality of bits for identifying a selected memory module, a second plurality of bits for identifying an address in the main memory means of said selected memory module, and a third plurality of bits for identifying a selected word in the auxiliary memory means of said selected module.
Claim 8
Dependent Claim
39 words
A memory module for use in a data processing system in accordance with claim 6 wherein each said memory module includes logic means responsive to said first plurality of bits of said address for determining said selected memory module.
Claim 9
Dependent Claim
57 words
A memory module for use in a data processing system in accordance with claim 7 wherein said logic means includes modifiable interconnections which are selectively arranged so that the positions of said first plurality of bits in said word addresses are allotted in accordance with the manner in which data in said auxiliary memory means are interleaved.
Claim 10
Dependent Claim
56 words
A memory module for use in a data processing system in accordance with claim 8 wherein said modifiable interconnections comprise a plurality of switch means, selected ones of said switch means being actuated so as to allot the positions of said first plurality of bits in accordance with the manner in which said data are interleaved.
Claim 11
Dependent Claim
57 words
A memory module for use in a data processing system in accordance with claim 8 wherein said modifiable interconnections comprise a plurality of movable jumper connections, the arrangement of said jumper connections being selected so as to allot the positions of said first plurality of bits in accordance with the manner in which said data are interleaved.
References Cited (Backward Citations)
US3445820A
Cited
US3588829A
Cited
US3588839A
Cited
US3699530A
Cited
US3693165A
Cited
US3764996A
Cited
US3829840A
Cited
US3820078A
Cited
US3810110A
Cited
US3866183A
Cited
US3840862A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |