Isolation between power supplies of an analog-digital circuit

Claim 2

A composite integrated circuit including two parallel wells that separate analog and digital blocks of the circuit, each well being of a conductivity type opposite to that of the substrate, and being respectively connected to a first terminal of a power supply source adapted to bias one of the two blocks, wherein a resistor is respectively interposed on the biasing link of each well from a first terminal of the biasing power supply of the digital or analog block to form with strong capacitances of the wells, a filtering switching noise.

Claim 3

The circuit of claim 1, wherein the resistor is a polysilicon resistor.

Claim 4

The circuit of claim 1, wherein the resistor is a resistor diffused in the well.

Claim 5

The circuit of claim 3, including a contact formed along an entire length of the substrate, interposed between both wells, and connected to a second terminal of the biasing power supply.

Claim 6

The circuit of claim 4, wherein the wells are of type N, the potential of the first power supply potential being the most positive potential of the power supply voltage.

Claim 7

The circuit of claim 4, wherein the wells are of type P, the potential of the first power supply potential being the most negative potential of the power supply voltage.

Claim 8

The circuit of claim 1, wherein said analog block includes an analog block well in said substrate containing at least one transistor and said digital block includes a digital block well in said substrate containing at least one transistor.

Claim 9

The circuit of claim 7, wherein said two parallel wells along with said analog block well and said digital block well are all disposed in the same surface of said substrate.

Claim 10

A composite integrated circuit comprising: an analog block; a digital block; a silicon substrate forming part of each block; an analog block well in said substrate containing at least one transistor; a digital block well in said substrate containing at least one transistor; two parallel-disposed wells in said substrate that separate analog and digital blocks and being of a conductivity type opposite to that of said substrate; said two wells being respectively coupled to a first terminal of a power supply source adapted to bias one of the two blocks; and a pair of resistors, each respectively interposed on the biasing link of each parallel-disposed well from the first terminal of the biasing power supply of the digital or analog block.

Claim 11

A composite integrated circuit comprising: an analog block; a digital block; a silicon substrate forming part of each block; an analog block well in said substrate containing at least one transistor; a digital block well in said substrate containing at least one transistor; two parallel-disposed wells in said substrate that separate analog and digital blocks and being of a conductivity type opposite to that of said substrate; said two wells being respectively coupled to a first terminal of a power supply source adapted to bias one of the two blocks; and a pair of resistors, each respectively interposed on the biasing link of each parallel-disposed well from the first terminal of the biasing power supply of the digital or analog block.

Claim 12

The circuit of claim 9, wherein the resistor is a polysilicon resistor.

Claim 13

The circuit of claim 9, wherein the resistor is a resistor defused in the well.

Claim 14

The circuit of claim 11, including a contact formed along a length of the substrate, interposed between both of said parallel disposed wells, and connected to a second terminal of the biasing power supply.

Claim 15

The circuit of claim 12, wherein the parallel-disposed wells are of type N, the potential of the first power supply being the most positive potential of the power supply voltage.

Claim 16

The circuit of claim 12, wherein the parallel-disposed wells are of type P, the potential of the first power supply being the most negative potential of the power supply voltage.

Claim 17

The circuit of claim 9, wherein said parallel-disposed wells, along with said analog block well and said digital block well are all disposed in the same surface of said silicon substrate.

Claim 18

The circuit of claim 9, wherein each resistor, forms with straight capacitances of the well of the two parallel-disposed wells, a filter for filtering switching noise.

Claim 19

A composite integrated circuit comprising: an analog block; a digital block; a silicon substrate forming part of each block; an analog block well in said substrate containing at least one transistor; at least one well in said substrate that separates the analog and digital blocks and being of a conductivity type opposite to that of said substrate; said separating well being coupled to a first terminal of a power supply source adapted to bias one of the two blocks; and at least one resistor interposed on the biasing link of the separating well from the first terminal of the biasing power supply of the digital or analog block.

Claim 20

A composite integrated circuit comprising: an analog block; a digital block; a silicon substrate forming part of each block; an analog block well in said substrate containing at least one transistor; at least one well in said substrate that separates the analog and digital blocks and being of a conductivity type opposite to that of said substrate; said separating well being coupled to a first terminal of a power supply source adapted to bias one of the two blocks; and at least one resistor interposed on the biasing link of the separating well from the first terminal of the biasing power supply of the digital or analog block.

Claim 21

The circuit of claim 17, wherein the resistor is adapted to form, with straight capacitances of the wells, a filter for filtering switching noise.

Claim 22

The circuit of claim 17, including two parallel-disposed wells in said substrate that separate analog and digital blocks and a related pair of resistors.

Claim 23

The circuit of claim 19, wherein the two parallel disposed wells along with the analog and digital block wells are all disposed in the same surface of the substrate.