Semiconductor integrated circuit suppressing noises due to short-circuit/substrate currents

Claim 2

A semiconductor integrated circuit comprising: a semiconductor substrate; at least one macrocell, each macrocell including CMOS elements formed on the substrate; and means for absorbing short-circuit current produced by the CMOS elements, the means formed on the substrate and including a high-impurity-concentration diffused region formed at the surface of the substrate and at least around one of the macrocells.

Claim 3

The circuit of claim 1, wherein said suppressing means further including a bias voltage supplying unit, electrically coupled to the diffused region to supply a bias voltage to the diffused region.

Claim 4

The circuit of claim 2, wherein the bias voltage supplying unit has a bias voltage supplying terminal that is independent of a terminal for supplying an operating voltage to the semiconductor elements.

Claim 5

The circuit of claim 2, wherein the bias voltage supplying unit commonly employs a terminal for supplying an operating voltage to the semiconductor elements, wherein an impedance of a line connecting the semiconductor elements to the terminal being substantially same or higher than that of a line for connecting the diffused region to the terminal.

Claim 6

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including CMOS elements formed on the substrate; voltage source means and grounding means, for supplying an operating voltage to the CMOS elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells for absorbing short-circuit current produced by the CMOS elements, the impurity concentration of the first diffused region being higher than that of the substrate; and a first means for supplying a first bias voltage to the first diffused region.

Claim 7

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including CMOS elements formed on the substrate; voltage source means and grounding means, for supplying an operating voltage to the CMOS elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells for absorbing short-circuit current produced by the CMOS elements, the impurity concentration of the first diffused region being higher than that of the substrate; and a first means for supplying a first bias voltage to the first diffused region.

Claim 8

The circuit of claim 5, further comprising: a second diffused region formed at the surface of the substrate around and separated from the first diffused region, the impurity concentration of the first diffused region being higher than that of the substrate; and a second means for supplying a second bias voltage to the second diffused region, wherein a conductivity type of one of the first and the second diffused regions is opposite to that of the substrate.

Claim 9

The circuit of claim 6, wherein the first and second diffused regions have different conductivity types.

Claim 10

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, an impurity concentration of the first diffused region being higher than that of the substrate; a first power line connected to the first diffused region and to the voltage source terminal; a second power line connected to the semiconductor elements and the voltage source terminal, the impedance of the second power line being higher than that of the first power line; and a third power line connected to the semiconductor elements and the grounding terminal.

Claim 11

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, an impurity concentration of the first diffused region being higher than that of the substrate; a first power line connected to the first diffused region and to the voltage source terminal; a second power line connected to the semiconductor elements and the voltage source terminal, the impedance of the second power line being higher than that of the first power line; and a third power line connected to the semiconductor elements and the grounding terminal.

Claim 12

The circuit of claim 8, wherein the second power line is connected to the first power line.

Claim 13

The circuit of claim 8, wherein the second power line is at least partly made of a polysilicon film.

Claim 14

The circuit of claim 8, wherein the first and second power lines are independent, and said voltage terminal comprises independent first and second voltage terminals connected to said first and second power respectively.

Claim 15

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, the impurity concentration of the first diffused region being higher than that of the substrate; a first power line connected to the first diffused region and the grounding terminal; a second power line connected to the semiconductor elements and the grounding terminal, the impedance of the second power line being higher than that of the first power line; and a third power line connected to the semiconductor elements and the voltage source terminal.

Claim 16

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, the impurity concentration of the first diffused region being higher than that of the substrate; a first power line connected to the first diffused region and the grounding terminal; a second power line connected to the semiconductor elements and the grounding terminal, the impedance of the second power line being higher than that of the first power line; and a third power line connected to the semiconductor elements and the voltage source terminal.

Claim 17

The circuit of claim 12, wherein the second power line is connected to the first power line.

Claim 18

The circuit of claim 12, wherein the second power line is at least partly made of a polysilicon film.

Claim 19

The circuit of claim 12, wherein the first and second power lines are independent, and said voltage terminal comprises independent first and second voltage terminals connected to said first and second power respectively.

Claim 20

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, an impurity concentration of the first diffused region being higher than that of the substrate; a second diffused region formed at the surface of the substrate around and separated from the first diffused region, an impurity concentration of the second diffused region being higher than that of the substrate; a first power line connected to the first diffused region and the voltage source terminal; a second power line connected to the semiconductor elements and the grounding terminal, the impedance of the second power line being higher than that of the first power line; a third power line connected to the second diffused region and the grounding terminal; and a fourth power line connected to the semiconductor elements and the grounding terminal, an impedance of the fourth power line being higher than that of the third power line.

Claim 21

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including semiconductor elements formed on the substrate; a voltage source terminal and a grounding terminal, for supplying an operating voltage to the semiconductor elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells, an impurity concentration of the first diffused region being higher than that of the substrate; a second diffused region formed at the surface of the substrate around and separated from the first diffused region, an impurity concentration of the second diffused region being higher than that of the substrate; a first power line connected to the first diffused region and the voltage source terminal; a second power line connected to the semiconductor elements and the grounding terminal, the impedance of the second power line being higher than that of the first power line; a third power line connected to the second diffused region and the grounding terminal; and a fourth power line connected to the semiconductor elements and the grounding terminal, an impedance of the fourth power line being higher than that of the third power line.

Claim 22

The circuit of claim 16, wherein the second power line is connected to the first power line, and the fourth power line is connected to the third power line.

Claim 23

The circuit of claim 16, wherein the second and fourth power lines are at least partly made of a polysilicon film.

Claim 24

The circuit of claim 16, wherein the first and second diffused regions have different conductivity types.

Claim 25

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including CMOS elements formed on the substrate; voltage source means and grounding means, for supplying an operating voltage to the CMOS elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells for absorbing short-circuit current produced by the CMOS elements, the impurity concentration of the first diffused region being higher than that of the substrate; and a first power line connected to the CMOS elements and the voltage source terminal; a second power line connected to the CMOS elements and the grounding terminal; and a third power line connected to the diffused region and one of the voltage source and grounding terminals.

Claim 26

A semiconductor integrated circuit comprising: a semiconductor substrate; macrocells each including CMOS elements formed on the substrate; voltage source means and grounding means, for supplying an operating voltage to the CMOS elements; a first diffused region formed at the surface of the substrate around and separated from at least one of the macrocells for absorbing short-circuit current produced by the CMOS elements, the impurity concentration of the first diffused region being higher than that of the substrate; and a first power line connected to the CMOS elements and the voltage source terminal; a second power line connected to the CMOS elements and the grounding terminal; and a third power line connected to the diffused region and one of the voltage source and grounding terminals.

Claim 27

The circuit of claim 20, further comprising: second diffused region formed at the surface of the substrate around and separated from the first diffused region, the impurity concentration of the first diffused region being higher than that of the substrate; and a fourth power line connected to the second diffused region and one of the grounding and voltage source terminals, which is not connected to said third power line, wherein a conductivity type of one of the first and the second diffused regions is opposite to that of the substrate.

Claim 28

The circuit of claim 21, wherein the first and second diffused regions have different conductivity types.