Low crosstalk type switching matrix of monolithic semiconductor device

Claim 2

In a low crosstalk type switching matrix of monolithic semiconductor device having a plurality of lateral type PNPN type switching elements (S ij ) arranged in matrix fashion comprising: a first conductivity type double layered substrate (11) including in its entirety a first layer (24) having high impurity concentration and a second layer (26) having low impurity concentration, said first and second layers being layered one upon another; a second conductivity type third layer (14) having low impurity concentration formed on said second layer in order to form said switching elements; second conductivity type buried layers (12) having high impurity concentration formed at the junction between said second and third layers and at respective crosspoints of the matrix; switch regions (14, 18, 20, 22) formed in said third layer over said buried layers at the respective crosspoints of the matrix, in order to form the switching elements; and first conductivity type isolation regions (28) formed in said third layer (14), enclosing each of said switch regions and contacting said second layer (26), said isolation regions (28) having outer peripheries; the improvement wherein: said substrate (11) has a low resistivity; and said third layer (14) includes second conductivity type separation regions (30) having low impurity concentration which form a separation distance (l 2 ) between the outer peripheries of said isolation regions (28) for reducing the signal crosstalk in cooperation with said low resistivity of said substrate (11), said separation distance (l 2 ) being about 10 microns.

Claim 3

A switching matrix according to claim 1 wherein said switch regions include a first electrode region (18), said third layer (14) includes a second electrode region, and a parasitic transistor (42) is formed by said first electrode region (18), said second electrode region, said second layer (26) and said isolation region (28) of each of said switch regions (14, 18, 20, 22); and further comprising second conductivity type compensation regions (32) having high impurity concentration located in said third layer (14) and contacting said buried layers (12), said compensation regions (32) enclosing said switch regions (14, 18, 20, 22) and being enclosed by said isolation regions (28), in order to reduce the current amplification factor of said parasitic transistor.

Claim 4

A switching matrix according to claim 2, wherein said third layer (14) includes second conductivity type regions (34) of low impurity concentration formed between said compensation regions (32) and said isolation regions (28), in order to improve the withstand voltage between said second electrode regions (14) and said isolation regions (28).

Claim 5

A switching matrix according to claim 1, wherein said switch regions are triode thyristors.

Claim 6

A switching matrix according to claim 1, wherein said switch regions are tetrode thyristors.

Claim 7

A switching matrix according to claim 1, wherein said switch regions are triode triacs.

Claim 8

A switching matrix according to claim 1, wherein said switch regions are tetrode triacs.

Claim 9

A switching matrix according to claim 1, wherein said switch regions are pentode triacs.

Claim 10

A low crosstalk type switching matrix of monolithic semiconductor device having a plurality of lateral type PNPN type switching elements arranged in matrix fashion, comprising: a double layered substrate (11) including in its entirety a first P + type layer (24) having high impurity concentration and a second P type layer (26) having low impurity concentration, said first and second layers being layered one upon another; a third N type layer (14) having low impurity concentration formed on said second P type layer (26) in order to form said switching elements; buried N + type layers (12) having high impurity concentration formed at the junction between said second P type layer (26) and said third N type layer (14) at respective crosspoints of the matrix; thyristor structures (14, 18, 20, 22) including an anode gate N type region (14) formed in said third N type layer (14) over said buried N + type layers (12), an anode P type region (18) and a cathode gate P type region (20) both of which are separately formed from the surface of said anode gate N type region (14) toward the inner portion thereof, and a cathode N + type region (22) having high impurity concentration formed from the surface of said cathode gate P type region (20) toward the inner portion thereof; isolation P + type regions (28) formed in said third N type layer (14) enclosing each of said thyristor structures so as to contact said second P type layer (26) but not to contact said buried N + type layers, said isolation P + type regions (28) having outer peripheries; separation N type regions (30) having low impurity concentration of said third N type layer (14) and which form a separation distance (l 2 ) of about 10 microns between the outer peripheries of said isolation P + type regions; a parasitic PNP type transistor (42) being formed by said anode P type region (18), said gate N type region (14), said second P type layer (26) and said isolation P + type region (28); compensation N + type regions (32) having high impurity concentration contacting said buried N + type layers (12) and enclosing said thyristor structures but being inside said isolation P + type regions (28) in said third N type layer (14), in order to reduce the current amplification factor of said parasitic PNP type transistor (42); and N type regions (34) of said third N type layer (14) formed between said compensation N + type regions (32) and said isolation P + type regions (28), in order to improve the withstand voltage between said gate N type regions (14) and said isolation P + type regions (28).

Claim 11

A low crosstalk type switching matrix of monolithic semiconductor device having a plurality of lateral type PNPN type switching elements arranged in matrix fashion, comprising: a double layered substrate (11) including in its entirety a first P + type layer (24) having high impurity concentration and a second P type layer (26) having low impurity concentration, said first and second layers being layered one upon another; a third N type layer (14) having low impurity concentration formed on said second P type layer (26) in order to form said switching elements; buried N + type layers (12) having high impurity concentration formed at the junction between said second P type layer (26) and said third N type layer (14) at respective crosspoints of the matrix; thyristor structures (14, 18, 20, 22) including an anode gate N type region (14) formed in said third N type layer (14) over said buried N + type layers (12), an anode P type region (18) and a cathode gate P type region (20) both of which are separately formed from the surface of said anode gate N type region (14) toward the inner portion thereof, and a cathode N + type region (22) having high impurity concentration formed from the surface of said cathode gate P type region (20) toward the inner portion thereof; isolation P + type regions (28) formed in said third N type layer (14) enclosing each of said thyristor structures so as to contact said second P type layer (26) but not to contact said buried N + type layers, said isolation P + type regions (28) having outer peripheries; separation N type regions (30) having low impurity concentration of said third N type layer (14) and which form a separation distance (l 2 ) of about 10 microns between the outer peripheries of said isolation P + type regions; a parasitic PNP type transistor (42) being formed by said anode P type region (18), said gate N type region (14), said second P type layer (26) and said isolation P + type region (28); compensation N + type regions (32) having high impurity concentration contacting said buried N + type layers (12) and enclosing said thyristor structures but being inside said isolation P + type regions (28) in said third N type layer (14), in order to reduce the current amplification factor of said parasitic PNP type transistor (42); and N type regions (34) of said third N type layer (14) formed between said compensation N + type regions (32) and said isolation P + type regions (28), in order to improve the withstand voltage between said gate N type regions (14) and said isolation P + type regions (28).

Claim 12

A low crosstalk type switching matrix of monolithic semiconductor device having a plurality of lateral type PNPN type switching elements arranged in a matrix, comprising: a double layered substrate (11) including in its entirety a first P + type layer (24) having high impurity concentration, said first and second layers being layered one upon another; a third N type layer (14) having low impurity concentration formed on said second P type layer (26) in order to form said switching elements; buried N + type layers (12) having high impurity concentration formed at the junction between said second P type layer (26) and said third N type layer (14) at respective crosspoints of the matrix; triac structures formed by a gate N type region (14) formed in said third N type layer (14) over said buried N + type layers (12), a first gate P type region (18) and a second gate P type region (20) both of which have low impurity concentration and are separately formed from the surface of said gate N type region (14) toward the inner portions thereof, and first and second N + type regions (56, 22) both of which have high impurity concentration and are formed from the surface of said first and second gate P type regions (18, 20) toward the inner portions thereof; isolation P + type regions (28) formed in said third N type layer (14) enclosing each of said triac structures so as to contact said second P type layer (26) but not to contact said buried N + type layers, said isolation P + type regions having outer peripheries; separation N type regions (34) having low impurity concentration of said third N type layer (14) and which form a separation distance (l 2 ) of about 10 microns between the outer peripheries of said isolation P + type regions (28); a parasitic PNP type transistor formed by said first and second gate P type regions (18,20), said gate N type region (14), said second P type layer (26) and said isolation P + type region (28); compensation N + type regions (32) having high impurity concentration contacting said buried N + type layers and enclosing said triac structures but being inside said isolation P + type regions in said third N type layer (14), in order to reduce the current amplification factor of said parasitic PNP type transistor; and N type regions (34) of said third N type layer (14) formed between said compensation N + type regions (32) and said isolation P + type regions (28), in order to improve the withstand voltage between said gate N type regions (14) and said isolation P + type regions (28).

Claim 13

A low crosstalk type switching matrix of monolithic semiconductor device having a plurality of lateral type PNPN type switching elements arranged in a matrix, comprising: a double layered substrate (11) including in its entirety a first P + type layer (24) having high impurity concentration, said first and second layers being layered one upon another; a third N type layer (14) having low impurity concentration formed on said second P type layer (26) in order to form said switching elements; buried N + type layers (12) having high impurity concentration formed at the junction between said second P type layer (26) and said third N type layer (14) at respective crosspoints of the matrix; triac structures formed by a gate N type region (14) formed in said third N type layer (14) over said buried N + type layers (12), a first gate P type region (18) and a second gate P type region (20) both of which have low impurity concentration and are separately formed from the surface of said gate N type region (14) toward the inner portions thereof, and first and second N + type regions (56, 22) both of which have high impurity concentration and are formed from the surface of said first and second gate P type regions (18, 20) toward the inner portions thereof; isolation P + type regions (28) formed in said third N type layer (14) enclosing each of said triac structures so as to contact said second P type layer (26) but not to contact said buried N + type layers, said isolation P + type regions having outer peripheries; separation N type regions (34) having low impurity concentration of said third N type layer (14) and which form a separation distance (l 2 ) of about 10 microns between the outer peripheries of said isolation P + type regions (28); a parasitic PNP type transistor formed by said first and second gate P type regions (18,20), said gate N type region (14), said second P type layer (26) and said isolation P + type region (28); compensation N + type regions (32) having high impurity concentration contacting said buried N + type layers and enclosing said triac structures but being inside said isolation P + type regions in said third N type layer (14), in order to reduce the current amplification factor of said parasitic PNP type transistor; and N type regions (34) of said third N type layer (14) formed between said compensation N + type regions (32) and said isolation P + type regions (28), in order to improve the withstand voltage between said gate N type regions (14) and said isolation P + type regions (28).

Claim 14

A switching matrix according to claim 1 wherein said separation regions (30) have a higher resistivity than said double layered substrate (11).

Claim 15

A switching matrix according to claim 9 wherein said double layered substrate 11 has a low resistivity, and said separation regions (30) have a high resistivity.

Claim 16

A switching matrix according to claim 10 wherein said double layered substrate 11 has a low resistivity, and said separation regions (30) have a high resistivity.