Semiconductor device and manufacturing method thereof

Claim 2

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate and having a first circuit region; a second impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a second circuit region; and a third impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a third circuit region, wherein said semiconductor substrate and said third impurity region are set to the same potential, said second impurity region is set to a potential different from that of said semiconductor substrate and said third impurity region, and said second impurity region is set to a potential different from that of said first impurity region.

Claim 3

The semiconductor device as recited in claim 1, wherein said semiconductor substrate and said third impurity region are set to a first potential of p type, said first impurity region is set to a second potential of n type higher than said first potential, and said second impurity region is set to a third potential of p type lower than said second potential.

Claim 4

The semiconductor device as recited in claim 1, wherein said semiconductor substrate and said third impurity region are set to a first potential of n type, said first impurity region is set to a second potential of p type lower than said first potential, and said second impurity region is set to a third potential of n type higher than said second potential.

Claim 5

The semiconductor device as recited in claim 1, wherein said first circuit region and said third circuit region form a peripheral circuit, and said second circuit region form a storing circuit region.

Claim 6

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate and having a first circuit region; a second impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a second circuit region; a third impurity region of the first conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate with a first side surface and a part of a bottom surface formed in said first impurity region and having a third circuit region; and a fourth impurity region of the second conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate so as to surround a second side surface and a part of said bottom surface of said third impurity region, wherein said semiconductor substrate and said third impurity region are set to the same potential, said first impurity region and said fourth impurity region are set to different potentials, and said second impurity region and said third impurity region are set to different potentials.

Claim 7

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate and having a first circuit region; a second impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a second circuit region; a third impurity region of the first conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate with a first side surface and a part of a bottom surface formed in said first impurity region and having a third circuit region; and a fourth impurity region of the second conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate so as to surround a second side surface and a part of said bottom surface of said third impurity region, wherein said semiconductor substrate and said third impurity region are set to the same potential, said first impurity region and said fourth impurity region are set to different potentials, and said second impurity region and said third impurity region are set to different potentials.

Claim 8

The semiconductor device as recited in claim 5, wherein said semiconductor substrate and said third impurity region are set to a first potential of p type, said first impurity region is set to a second potential of an type higher than said first potential, said second impurity region is set to a third potential of p type lower than said second potential, and said fourth impurity region is set to a fourth potential of n type higher than said first potential.

Claim 9

The semiconductor device as recited in claim 5, wherein said semiconductor substrate and said third impurity region are set to a first potential of n type, said first impurity region is set to a second potential of p type lower than said first potential, said second impurity region is set to a third potential of n type higher than said second potential, and said fourth impurity region is set to a fourth potential of p type lower than said first potential.

Claim 10

The semiconductor device as recited in claim 5, wherein said first circuit region and said third circuit region form a peripheral circuit, and said second circuit region form a storing circuit region.

Claim 11

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity layer of a second conductivity type formed at a predetermined depth from a main surface of said semiconductor substrate; a second impurity layer of the first conductivity type formed in contact with an upper surface of said first impurity layer; a third impurity layer of the second conductivity type formed in contact with an upper surface of said second impurity layer and electrically connected to said first impurity layer; and a fourth impurity layer of the first conductivity type formed in contact with an upper surface of said third impurity layer and electrically connected to said second impurity layer, wherein said first impurity layer and said third impurity layer are set to a potential different from said second impurity layer and said fourth impurity layer.

Claim 12

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity layer of a second conductivity type formed at a predetermined depth from a main surface of said semiconductor substrate; a second impurity layer of the first conductivity type formed in contact with an upper surface of said first impurity layer; a third impurity layer of the second conductivity type formed in contact with an upper surface of said second impurity layer and electrically connected to said first impurity layer; and a fourth impurity layer of the first conductivity type formed in contact with an upper surface of said third impurity layer and electrically connected to said second impurity layer, wherein said first impurity layer and said third impurity layer are set to a potential different from said second impurity layer and said fourth impurity layer.

Claim 13

The semiconductor device as recited in claim 9, wherein said first impurity layer and said third impurity layer are set to a ground potential, and said second impurity layer and said fourth impurity layer are set to a power supply potential.

Claim 14

The semiconductor device as recited in claim 9, comprising an impurity active region in which a semiconductor element is formed between the main surface of said semiconductor substrate and said fourth impurity layer, said impurity active region includes a fifth impurity layer of the first conductivity type electrically connected to said fourth impurity layer, and a sixth impurity layer of the second conductivity type electrically connected to said third impurity layer.

Claim 15

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region; and an impurity layer of the second conductivity type formed at a predetermined depth from the main surface of said semiconductor region so as to extend within both said first impurity region and said second impurity region, wherein said first impurity region and said second impurity region are set to different potentials, and said second impurity region and said impurity layer are set to the same potentials.

Claim 16

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region; and an impurity layer of the second conductivity type formed at a predetermined depth from the main surface of said semiconductor region so as to extend within both said first impurity region and said second impurity region, wherein said first impurity region and said second impurity region are set to different potentials, and said second impurity region and said impurity layer are set to the same potentials.

Claim 17

The semiconductor device as recited in claim 12, wherein a plurality of said impurity layers are disposed at different positions in the depth direction.

Claim 18

The semiconductor device as recited in claim 12, wherein said first impurity region is set to a ground potential, and said impurity layer is set to a power supply potential.

Claim 19

The semiconductor device as recited in claim 12, wherein said first impurity region is set to a power supply potential, and said impurity layer is set to a potential lower than said power supply potential.

Claim 20

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a first depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region at a second depth greater than said first depth from the main surface of said semiconductor region; and a third impurity region of the second conductivity type formed at a depth between said first depth and said second depth to extend within both said semiconductor region and said second impurity region, wherein said semiconductor region and said third impurity region are set to different potentials.

Claim 21

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a first depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region at a second depth greater than said first depth from the main surface of said semiconductor region; and a third impurity region of the second conductivity type formed at a depth between said first depth and said second depth to extend within both said semiconductor region and said second impurity region, wherein said semiconductor region and said third impurity region are set to different potentials.

Claim 22

The semiconductor device as recited in claim 16, wherein said semiconductor region is set to a ground potential, and said third impurity region is set to a power supply potential.

Claim 23

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region so as to longitudinally extend in parallel with said main surface; a second impurity region of a second conductivity type formed adjacent to said first impurity region so as to extend in parallel with said main surface; a third impurity region of the first conductivity type formed adjacent to said second impurity region so as to extend in parallel with said main surface; and a fourth impurity region of the second conductivity type formed adjacent to said third impurity region so as to extend in parallel with said main surface, wherein said first impurity region and said third impurity region are electrically connected at respective first end sides, said second impurity region and said fourth impurity region are electrically connected to said first impurity region and said third impurity region at a respective second sides thereof, said respective first end sides being respectively opposite said respective second sides, and said first impurity region and said third impurity region are set to a potential different from said second impurity region and said fourth impurity region, wherein, a PN junction is formed between the first impurity region and the second impurity region under a negative voltage bias.

Claim 24

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region so as to longitudinally extend in parallel with said main surface; a second impurity region of a second conductivity type formed adjacent to said first impurity region so as to extend in parallel with said main surface; a third impurity region of the first conductivity type formed adjacent to said second impurity region so as to extend in parallel with said main surface; and a fourth impurity region of the second conductivity type formed adjacent to said third impurity region so as to extend in parallel with said main surface, wherein said first impurity region and said third impurity region are electrically connected at respective first end sides, said second impurity region and said fourth impurity region are electrically connected to said first impurity region and said third impurity region at a respective second sides thereof, said respective first end sides being respectively opposite said respective second sides, and said first impurity region and said third impurity region are set to a potential different from said second impurity region and said fourth impurity region, wherein, a PN junction is formed between the first impurity region and the second impurity region under a negative voltage bias.

Claim 25

The semiconductor device as recited in claim 18, wherein said first impurity region and said third impurity region are set to a ground potential, and said second impurity region and said fourth impurity region are set to a power supply potential.

Claim 26

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed extending within said semiconductor region and said first impurity region and extending longitudinally in parallel with the main surface of said semiconductor region; and a third impurity region of the second conductivity type formed adjacent to said first impurity region so as to extend longitudinally in parallel with said second impurity region, wherein said second impurity region and said third impurity region are electrically connected at respective end portions, and said first impurity region is set to a potential different from said second impurity region and said third impurity region.

Claim 27

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed extending within said semiconductor region and said first impurity region and extending longitudinally in parallel with the main surface of said semiconductor region; and a third impurity region of the second conductivity type formed adjacent to said first impurity region so as to extend longitudinally in parallel with said second impurity region, wherein said second impurity region and said third impurity region are electrically connected at respective end portions, and said first impurity region is set to a potential different from said second impurity region and said third impurity region.

Claim 28

The semiconductor device as recited in claim 20, wherein said first impurity region is set to a ground potential, and said second impurity region and said third impurity region are set to a power supply potential.

Claim 29

The semiconductor device as recited in claim 20, wherein a plurality of said second impurity regions are disposed in parallel.

Claim 30

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region; a third impurity region of the second conductivity type formed in contact with a lower surface of said first impurity region and said second impurity region; and a fourth impurity region of the second conductivity type formed so as to extend over said first impurity region and said third impurity region, wherein said first impurity region and said fourth impurity region are set to different potentials.

Claim 31

A semiconductor device, comprising: a semiconductor region of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor region; a second impurity region of a second conductivity type formed adjacent to said first impurity region; a third impurity region of the second conductivity type formed in contact with a lower surface of said first impurity region and said second impurity region; and a fourth impurity region of the second conductivity type formed so as to extend over said first impurity region and said third impurity region, wherein said first impurity region and said fourth impurity region are set to different potentials.

Claim 32

The semiconductor device as recited in claim 23, wherein said first impurity region is set to a ground potential, and said fourth impurity region is set to a power supply potential.

Claim 33

The semiconductor device as recited in claim 23, wherein a plurality of said fourth impurity regions are disposed in parallel.

Claim 34

A semiconductor device, comprising: a source/drain region; a capacitor; an impurity layer of a first conductivity type having a main surface; a first active region of a second conductivity type forming the source/drain region of a transistor and extending from the main surface to a first depth within the impurity layer; and a second active region of the second conductivity type electrically connected to the source/drain region which forms the capacitor with the impurity layer and extending from the main surface to a second depth, greater than the first depth, within the impurity layer; wherein the impurity layer and the second active region are set to different potentials.

Claim 35

A semiconductor device, comprising: a source/drain region; a capacitor; an impurity layer of a first conductivity type having a main surface; a first active region of a second conductivity type forming the source/drain region of a transistor and extending from the main surface to a first depth within the impurity layer; and a second active region of the second conductivity type electrically connected to the source/drain region which forms the capacitor with the impurity layer and extending from the main surface to a second depth, greater than the first depth, within the impurity layer; wherein the impurity layer and the second active region are set to different potentials.

Claim 36

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate; a second impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a second circuit region; a third impurity region of the first conductivity type formed adjacent to said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a first circuit region; and a fourth impurity region of the second conductivity type formed adjacent to said third impurity region to have a predetermined depth from the main surface of said semiconductor substrate so as to surround and contact a part of a bottom surface of said third impurity region and having a third circuit region, wherein said first impurity region and said second impurity region are set to different potentials, and said third impurity region and said fourth impurity region are set to different potentials.

Claim 37

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate; a second impurity region of the first conductivity type formed in said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a second circuit region; a third impurity region of the first conductivity type formed adjacent to said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a first circuit region; and a fourth impurity region of the second conductivity type formed adjacent to said third impurity region to have a predetermined depth from the main surface of said semiconductor substrate so as to surround and contact a part of a bottom surface of said third impurity region and having a third circuit region, wherein said first impurity region and said second impurity region are set to different potentials, and said third impurity region and said fourth impurity region are set to different potentials.

Claim 38

The semiconductor device as recited in claim 27, wherein said first impurity region is set to a first potential of n type, said fourth impurity region is set to a second potential of an type, said second impurity region is set to a third potential of p type lower than said first potential, and said third impurity region is set to a fourth potential of p type lower than said second potential.

Claim 39

The semiconductor device as recited in claim 27, wherein said first circuit region and said third circuit region form a peripheral circuit region, and said second circuit region form a storing circuit region.

Claim 40

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate and having a second circuit region; a second impurity region of a second conductivity type formed adjacent to said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate so as to surround a part of a bottom surface of said first impurity region; a third impurity region of the second conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate and having a third circuit region; and a fourth impurity region of the first conductivity type formed in said third impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a first circuit region, wherein said first impurity region and said second impurity region are set to different potentials, and said third impurity region and said fourth impurity region are set to different potentials.

Claim 41

A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a first impurity region of the first conductivity type formed to have a predetermined depth from a main surface of said semiconductor substrate and having a second circuit region; a second impurity region of a second conductivity type formed adjacent to said first impurity region to have a predetermined depth from the main surface of said semiconductor substrate so as to surround a part of a bottom surface of said first impurity region; a third impurity region of the second conductivity type formed to have a predetermined depth from the main surface of said semiconductor substrate and having a third circuit region; and a fourth impurity region of the first conductivity type formed in said third impurity region to have a predetermined depth from the main surface of said semiconductor substrate and having a first circuit region, wherein said first impurity region and said second impurity region are set to different potentials, and said third impurity region and said fourth impurity region are set to different potentials.

Claim 42

The semiconductor device as related in claim 30, wherein said second impurity region is set to a first potential of n type, said third impurity region is set to a second potential of n type, said first impurity region is set to a third potential of p type lower than said first potential and, said fourth impurity region is set to a fourth potential of p type lower than said second potential.

Claim 43

The semiconductor device as recited in claim 30, wherein said first circuit region and said third circuit region form a peripheral circuit region, and said second circuit region form a storing circuit region.

Claim 46

The semiconductor device according to claim 1, wherein the first, second and third impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 47

The semiconductor device according to claim 16, wherein: the first, second and third impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 48

The semiconductor device according to claim 20, wherein: the first, second and third impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 49

The semiconductor device according to claim 5, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 50

The semiconductor device according to claim 9, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 51

The semiconductor device according to claim 18, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation.

Claim 52

The semiconductor device according to claim 23, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 53

The semiconductor device according to claim 27, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 54

The semiconductor device according to claim 30, wherein: the first, second, third and fourth impurity regions are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 55

The semiconductor device according to claim 12, wherein: the first impurity region, the second impurity region, and the impurity layer are each formed by a respective high ion energy implantation of a corresponding impurity.

Claim 56

The semiconductor device according to claim 26, wherein: the second active region is formed by high ion energy implantation.