US6147890A
Expired / Lapsed
US
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FPGA with embedded content-addressable memory
Assignee: Kawasaki Microelectronics Inc
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Filing: 1998-10-05
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Granted: 2000-11-14
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Expires: 2018-10-05
Abstract
Abstract Content Addressable Memory (CAM) core is integrated and interfaced with a configurable logic core (e.g., FPGA) on a single integrated circuit (IC) chip to permit a user to change algorithms for and to tailor word length to a particular application. Significant improvements in fetch times and overhead are achieved. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.
Inventors
- 👤 Keiichi Kawana
- 👤 Michael D. Rostoker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; G; G11; G11C; G11C15/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
55 words
A memory device, comprising: an integrated circuit (IC) chip; a Content Addressable Memory (CAM) "core" block integrated onto the IC chip; and user-configurable logic integrated onto the IC chip; wherein the user-configurable logic is capable of being configured to establish one of a variety of word lengths for words stored in the memory core block.
Claim 2
Dependent Claim
55 words
A memory device, comprising: an integrated circuit (IC) chip; a Content Addressable Memory (CAM) "core" block integrated onto the IC chip; and user-configurable logic integrated onto the IC chip; wherein the user-configurable logic is capable of being configured to establish one of a variety of word lengths for words stored in the memory core block.
Claim 3
Dependent Claim
20 words
The memory device, according to claim 1, wherein: the user-configurable logic is implemented as a Field Programmable Gate Array (FPGA).
Claim 4
Dependent Claim
40 words
The memory device, according to claim 1, wherein: a portion of the user-configurable logic is provided with inputs and outputs to the CAM being provided as outputs and inputs, respectively, to programmable cells in other portions of the user-configurable logic.
Claim 5
Independent Claim
51 words
A method of detecting occurrences of data in a memory array, comprising: integrating a content addressable memory (CAM) core and a user-configurable logic core on a single integrated circuit (IC) chip; and configuring the user-configurable logic to establish one of a variety of word lengths for words stored in the memory.
Claim 6
Independent Claim
51 words
A method of detecting occurrences of data in a memory array, comprising: integrating a content addressable memory (CAM) core and a user-configurable logic core on a single integrated circuit (IC) chip; and configuring the user-configurable logic to establish one of a variety of word lengths for words stored in the memory.
Claim 7
Independent Claim
56 words
A method of data compression comprising: integrating a content addressable memory (CAM) core and a user-configurable logic core on a single integrated circuit (IC) chip; searching matching data bytes in the CAM; and configuring the user-configurable logic to format results of the searching into a form suited to one of a variety of data compression algorithms.
Claim 8
Independent Claim
56 words
A method of data compression comprising: integrating a content addressable memory (CAM) core and a user-configurable logic core on a single integrated circuit (IC) chip; searching matching data bytes in the CAM; and configuring the user-configurable logic to format results of the searching into a form suited to one of a variety of data compression algorithms.
Claim 9
Dependent Claim
58 words
An electronic system incorporating at least one integrated circuit (IC chip), said IC chip comprising: a Content Addressable Memory "core" block integrated onto the IC chip; and user-configurable logic integrated onto the IC chip; wherein the user-configurable logic is capable to be configured to establish one of a variety of word lengths for words stored in the memory.
Claim 10
Dependent Claim
58 words
An electronic system incorporating at least one integrated circuit (IC chip), said IC chip comprising: a Content Addressable Memory "core" block integrated onto the IC chip; and user-configurable logic integrated onto the IC chip; wherein the user-configurable logic is capable to be configured to establish one of a variety of word lengths for words stored in the memory.
Claim 11
Dependent Claim
32 words
The electronic system, according to claim 6, wherein the electronic system is selected from the group consisting of general-purpose computer, telecommunication device, network device, consumer device, receiver, recorder, display device, and vehicle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |