Nonvolatile SRAM cells and cell arrays

Claim 2

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said second programmable memory element is substantially identical to said fist programmable memory element.

Claim 3

The memory cell of claim 1 wherein said sensing node of said memory cell in a first state is at a level about equal to said first source, and said sensing node in a second state is at a level about equal to said second source.

Claim 4

The memory cell of claim 1 wherein said first programmable memory element and second programmable memory element are nonvolatile.

Claim 5

The memory cell of claim 1 wherein said first programmable memory element and said second programmable memory element and said second programmable memory element are one-time programmable.

Claim 6

A programmable logic device with a memory cell as recited in claim 1.

Claim 7

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said sensing node of said memory cell in a first state is at a level about equal to said first source, and said sensing node in a second state is at a level about equal to said second source, and in said first state, said first programmable memory element is programmably configured to couple said first voltage source to said sensing node, and said second programmable memory element is configured to decouple said second voltage source from said sensing node.

Claim 8

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said sensing node of said memory cell in a first state is at a level about equal to said first source, and said sensing node in a second state is at a level about equal to said second source, and in said first state, said first programmable memory element is programmably configured to couple said first voltage source to said sensing node, and said second programmable memory element is configured to decouple said second voltage source from said sensing node.

Claim 9

The memory cell of claim 6 wherein in said first state, said memory cell has no substantial power consumption.

Claim 10

The memory cell of claim 6 wherein in said second state, said memory cell has no static current flow.

Claim 11

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a sensing programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said sensing node of said memory cell in a first state is at a level about equal to said first source, and said sensing node in a second state is at a level about equal to said second source, and in said second state, said first programmable memory element is programmable configured to decouple said first voltage source form said sensing node, and said second programmable memory element is configured to couple said second voltage source to said sensing node.

Claim 12

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a sensing programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said sensing node of said memory cell in a first state is at a level about equal to said first source, and said sensing node in a second state is at a level about equal to said second source, and in said second state, said first programmable memory element is programmable configured to decouple said first voltage source form said sensing node, and said second programmable memory element is configured to couple said second voltage source to said sensing node.

Claim 13

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said first programmable memory element and said second programmable memory element are activated by a control signal, said control signal coupled to a gate of said first programmable memory element and coupled to a gate of said second programmable memory element.

Claim 14

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said first programmable memory element and said second programmable memory element are activated by a control signal, said control signal coupled to a gate of said first programmable memory element and coupled to a gate of said second programmable memory element.

Claim 15

The memory device of claim 10 wherein said first programmable memory element and second programmable memory element are EEPROM memory devices.

Claim 16

A system with a memory cell as recited in claim 10.

Claim 17

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said first programmable memory element is activated by a first control signal, coupled to a gate of said first programmable memory element, and wherein said second programmable memory element is activated by a second control signal, coupled to a gate of said second programmable memory element.

Claim 18

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source, wherein said first programmable memory element is activated by a first control signal, coupled to a gate of said first programmable memory element, and wherein said second programmable memory element is activated by a second control signal, coupled to a gate of said second programmable memory element.

Claim 19

The memory device of claim 13 wherein said first programmable memory element and second programmable memory element are Flash EEPROM memory devices.

Claim 20

A memory integrated circuit with a memory cell as recited in claim 13.

Claim 21

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; a third voltage source; and a select transistor, coupled between said sensing node and said third voltage source, said select transistor selectively couples said third voltage source to a tunnel dielectric source shared by said first programmable memory element and second programmable memory element.

Claim 22

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; a third voltage source; and a select transistor, coupled between said sensing node and said third voltage source, said select transistor selectively couples said third voltage source to a tunnel dielectric source shared by said first programmable memory element and second programmable memory element.

Claim 23

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; and wherein said memory cell is coupled to a gate of a pass transistor, wherein said pass transistor couples or decouples a global horizontal conductor to a global vertical conductor based on a stored state of said memory cell.

Claim 24

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; and wherein said memory cell is coupled to a gate of a pass transistor, wherein said pass transistor couples or decouples a global horizontal conductor to a global vertical conductor based on a stored state of said memory cell.

Claim 25

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node wherein said first programmable memory element comprises: a first state wherein said first programmable memory element couples said first voltage source to said sensing node; and a second state wherein said first programmable memory element decouples said first voltage source from said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source.

Claim 26

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node wherein said first programmable memory element comprises: a first state wherein said first programmable memory element couples said first voltage source to said sensing node; and a second state wherein said first programmable memory element decouples said first voltage source from said sensing node; and a second programmable memory element, coupled between said sensing node and a second voltage source.

Claim 27

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; a first control signal, coupled to said first programmable memory element, said first control signal activating a stored state of said first programmable memory element; and a second control signal, coupled to said second programmable memory element, said second control signal activating a stored state of said second programmable memory element.

Claim 28

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; a first control signal, coupled to said first programmable memory element, said first control signal activating a stored state of said first programmable memory element; and a second control signal, coupled to said second programmable memory element, said second control signal activating a stored state of said second programmable memory element.

Claim 29

The memory device of claim 19 wherein said first programmable memory element and second programmable memory element are floating gate memory devices.

Claim 30

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; and a tunnel dielectric source, coupled between said first programmable memory element and second programmable memory element, wherein said tunnel dielectric source is shared by said first programmable memory element and second programmable memory element.

Claim 31

A memory cell for an integrated circuit comprising: a first voltage source; a second voltage source, said second voltage source at a voltage level below a voltage level of said first voltage source; a sensing node; a first programmable memory element, coupled between said first voltage source and said sensing node; a second programmable memory element, coupled between said sensing node and a second voltage source; and a tunnel dielectric source, coupled between said first programmable memory element and second programmable memory element, wherein said tunnel dielectric source is shared by said first programmable memory element and second programmable memory element.

Claim 32

A memory cell for an integrated circuit comprising: an output node, for providing an output of said memory cell; a first voltage source; a second voltage source, said second voltage source at a level below said first voltage source; a first control voltage; a second control voltage; an erase node; a first programmable memory element, coupled between said first voltage source and said output node, wherein said first control voltage is coupled to a gate of said first programmable memory element; a second programmable memory element, coupled between said output node and said second voltage source, said second programmable memory element is substantially similar to said first programmable memory element, wherein said second control voltage is coupled to a gate of said second programmable memory element; a tunnel dielectric source, coupled to said erase node and shared by said first programmable memory element and said second programmable memory element, wherein said tunnel dielectric source passes electrons between said erase node and a floating gate of said first programmable memory element through a first dielectric and between said erase node and a floating gate of said second programmable memory element through a second dielectric; and a select device, coupled between said output node and said erase node, wherein said erase node provides a voltage through said select device to said tunnel dielectric source.

Claim 33

A memory cell for an integrated circuit comprising: an output node, for providing an output of said memory cell; a first voltage source; a second voltage source, said second voltage source at a level below said first voltage source; a first control voltage; a second control voltage; an erase node; a first programmable memory element, coupled between said first voltage source and said output node, wherein said first control voltage is coupled to a gate of said first programmable memory element; a second programmable memory element, coupled between said output node and said second voltage source, said second programmable memory element is substantially similar to said first programmable memory element, wherein said second control voltage is coupled to a gate of said second programmable memory element; a tunnel dielectric source, coupled to said erase node and shared by said first programmable memory element and said second programmable memory element, wherein said tunnel dielectric source passes electrons between said erase node and a floating gate of said first programmable memory element through a first dielectric and between said erase node and a floating gate of said second programmable memory element through a second dielectric; and a select device, coupled between said output node and said erase node, wherein said erase node provides a voltage through said select device to said tunnel dielectric source.

Claim 34

A memory cell for an integrated circuit comprising: a first Flash memory device, coupled between a first source and a sensing node; a second Flash memory device, coupled between said sensing node and a second source; a third Flash memory device, coupled between a program node and a erase node, said third Flash memory device sharing a floating gate with said first Flash memory device; and a fourth Flash memory device, coupled between said erase node and said program node, said fourth Flash memory device sharing a floating gate with said second Flash memory device.

Claim 35

A memory cell for an integrated circuit comprising: a first Flash memory device, coupled between a first source and a sensing node; a second Flash memory device, coupled between said sensing node and a second source; a third Flash memory device, coupled between a program node and a erase node, said third Flash memory device sharing a floating gate with said first Flash memory device; and a fourth Flash memory device, coupled between said erase node and said program node, said fourth Flash memory device sharing a floating gate with said second Flash memory device.

Claim 36

A memory cell for an integrated circuit comprising: a first source; a second source, said second source at a level below a level of said first source; a sensing node, for providing an output of said memory cell, wherein said output of said memory cell in a first state is at a level about equal to said first source, and said output in a second state is at a level about equal to said second source; a first EEPROM device, coupled between said first source and said sensing node, wherein a gate of said first EEPROM device is coupled to a control node; a second EEPROM device, coupled between said sensing node and a second source, wherein said second EEPROM device is substantially identical to said first EEPROM device, wherein a gate of said second EEPROM device is coupled to said control node; a first NMOS device, coupled between a first erase source and a floating gate of said first EEPROM device, wherein a gate of said first NMOS transistor is coupled to a select node; and a second NMOS device, coupled between a second erase source and a floating gate of said second EEPROM device, wherein a gate of said second NMOS transistor is coupled to said select node.

Claim 37

A memory cell for an integrated circuit comprising: a first source; a second source, said second source at a level below a level of said first source; a sensing node, for providing an output of said memory cell, wherein said output of said memory cell in a first state is at a level about equal to said first source, and said output in a second state is at a level about equal to said second source; a first EEPROM device, coupled between said first source and said sensing node, wherein a gate of said first EEPROM device is coupled to a control node; a second EEPROM device, coupled between said sensing node and a second source, wherein said second EEPROM device is substantially identical to said first EEPROM device, wherein a gate of said second EEPROM device is coupled to said control node; a first NMOS device, coupled between a first erase source and a floating gate of said first EEPROM device, wherein a gate of said first NMOS transistor is coupled to a select node; and a second NMOS device, coupled between a second erase source and a floating gate of said second EEPROM device, wherein a gate of said second NMOS transistor is coupled to said select node.

Claim 38

A memory cell for an integrated circuit comprising: a first source; a second source, said second source at a level below a level of said first source; a tunnel diode, said tunnel diode is a source of electrons; an erase node, coupled to said tunnel diode, said erase node provides voltages to said tunnel diode; a sensing node, for providing an output of said memory cell, wherein said output of said memory cell in a first state is at a level about equal to said first source, and said output in a second state is at a level about equal to said second source; a first Flash EEPROM device, coupled between said first source and said sensing node, wherein a gate of said first Flash EEPROM device is coupled to a first control node; a second Flash EEPROM device, coupled between said sensing node and a second source, wherein a gate of said second Flash EEPROM device is coupled to a second control node; a first tunnel dielectric, coupled between a floating gate of said first Flash EEPROM device and said tunnel diode, wherein said first tunnel dielectric passes electrons between said tunnel diode and said floating gate of said first Flash EEPROM device; and a second tunnel dielectric, coupled between a floating gate of said second Flash EEPROM device and said tunnel diode, wherein said second tunnel dielectric passes electrons between said tunnel diode and said floating gate of said second Flash EEPROM device.

Claim 39

A memory cell for an integrated circuit comprising: a first source; a second source, said second source at a level below a level of said first source; a tunnel diode, said tunnel diode is a source of electrons; an erase node, coupled to said tunnel diode, said erase node provides voltages to said tunnel diode; a sensing node, for providing an output of said memory cell, wherein said output of said memory cell in a first state is at a level about equal to said first source, and said output in a second state is at a level about equal to said second source; a first Flash EEPROM device, coupled between said first source and said sensing node, wherein a gate of said first Flash EEPROM device is coupled to a first control node; a second Flash EEPROM device, coupled between said sensing node and a second source, wherein a gate of said second Flash EEPROM device is coupled to a second control node; a first tunnel dielectric, coupled between a floating gate of said first Flash EEPROM device and said tunnel diode, wherein said first tunnel dielectric passes electrons between said tunnel diode and said floating gate of said first Flash EEPROM device; and a second tunnel dielectric, coupled between a floating gate of said second Flash EEPROM device and said tunnel diode, wherein said second tunnel dielectric passes electrons between said tunnel diode and said floating gate of said second Flash EEPROM device.