US6144581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
pMOS EEPROM non-volatile data storage
Assignee: California Institute of Technology
•
Filing: 1998-11-30
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Granted: 2000-11-07
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Expires: 2018-11-30
Abstract
Abstract A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
Inventors
- 👤 Christopher J. Diorio
- 👤 Carver A. Mead
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:05
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
235 words
An integrated circuit comprising: a microprocessor circuit; a plurality of pMOS EEPROMS for non-volatile storage of data on said integrated circuit, wherein the pMOS EEPROMS comprise: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a first conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; and a second conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel region through said first insulating layer onto said floating gate; and means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
Claim 2
Dependent Claim
235 words
An integrated circuit comprising: a microprocessor circuit; a plurality of pMOS EEPROMS for non-volatile storage of data on said integrated circuit, wherein the pMOS EEPROMS comprise: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a first conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; and a second conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel region through said first insulating layer onto said floating gate; and means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
Claim 3
Dependent Claim
25 words
The integrated circuit according to claim 1 including means for simultaneously causing electron injection onto said floating gate and electron tunneling from said floating gate.
Claim 4
Dependent Claim
209 words
An integrated circuit comprising: a microprocessor circuit; a plurality of pMOS EEPROMS for non-volatile storage of data on said integrated circuit, wherein the pMOS EEPROMS comprise: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a second insulating layer disposed over said floating gate; a gate conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel region through said first insulating layer into said floating gate; and means for selectively causing electrons to tunnel from said floating gate to said n+ type well region through said first insulating layer; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
Claim 5
Dependent Claim
209 words
An integrated circuit comprising: a microprocessor circuit; a plurality of pMOS EEPROMS for non-volatile storage of data on said integrated circuit, wherein the pMOS EEPROMS comprise: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a second insulating layer disposed over said floating gate; a gate conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel region through said first insulating layer into said floating gate; and means for selectively causing electrons to tunnel from said floating gate to said n+ type well region through said first insulating layer; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
Claim 6
Dependent Claim
20 words
An integrated circuit, apparatus according to claim 3 including means for simultaneously causing said electron injection and said electron tunneling.
Claim 7
Dependent Claim
214 words
An integrated circuit, apparatus comprising: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a first conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a gate conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; and means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
Claim 8
Dependent Claim
214 words
An integrated circuit, apparatus comprising: a p- type region disposed within a semiconductor substrate; an n- type well region disposed within said p- type region; a first p+ type region disposed within said n- type well region; a second p+ type region disposed within said n- type well region; an n+ type well region disposed within said n- type region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said n- type well region between said first p+ type region and said second p+ type region; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a first conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a gate conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; and means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling; and means for storing and retrieving a BIOS for use with said microprocessor circuit in said pMOS EEPROMS.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |