Semiconductor structure for long term learning

Claim 2

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel and separated from said channel by an insulator, a portion of said floating gate also disposed over said n- type region; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 3

The semiconductor structure according to claim 1 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

Claim 4

The semiconductor structure according to claim 1 wherein said insulator is a layer of gate oxide.

Claim 5

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel including a region additionally p-doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed both above said channel and above a portion of said n- type region and separated from said channel and said portion of said n- type region by an insulator; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 6

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel including a region additionally p-doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed both above said channel and above a portion of said n- type region and separated from said channel and said portion of said n- type region by an insulator; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 7

The semiconductor structure according to claim 4 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

Claim 8

The semiconductor structure according to claim 4 wherein said insulator is a layer of gate oxide.

Claim 9

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; an n+ type source region disposed in said p- type region; an n+ type drain region disposed in said p- type region; an n- type tunneling junction region disposed in said p- type region, said n- type tunneling junction region including an n+ doped plug region surrounded by a lightly doped n- region within said p- type region; a channel disposed between said source region and said drain region, said channel including an additionally p doped region having an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel and over said n- type tunneling junction region, said floating gate disposed adjacent to at least one edge of each of said drain region, said source region and said n+ doped plug region, and separated from said semiconductor substrate by a gate oxide under a portion of said floating gate including at least where it is adjacent to an edge of each of said drain region, said source region and said n+ doped plug region; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacity coupled to said floating gate; means for applying a first positive potential to said drain region with respect to said p- type region to reverse bias said drain region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said drain region and said p- type region; means for capacity coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said source region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said tunneling junction region, said fourth potential being positive with respect to said floating gate.

Claim 10

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; an n+ type source region disposed in said p- type region; an n+ type drain region disposed in said p- type region; an n- type tunneling junction region disposed in said p- type region, said n- type tunneling junction region including an n+ doped plug region surrounded by a lightly doped n- region within said p- type region; a channel disposed between said source region and said drain region, said channel including an additionally p doped region having an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel and over said n- type tunneling junction region, said floating gate disposed adjacent to at least one edge of each of said drain region, said source region and said n+ doped plug region, and separated from said semiconductor substrate by a gate oxide under a portion of said floating gate including at least where it is adjacent to an edge of each of said drain region, said source region and said n+ doped plug region; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacity coupled to said floating gate; means for applying a first positive potential to said drain region with respect to said p- type region to reverse bias said drain region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said drain region and said p- type region; means for capacity coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said source region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said tunneling junction region, said fourth potential being positive with respect to said floating gate.

Claim 11

The semiconductor structure according to claim 7 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

Claim 12

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and separated from said channel and from said n- type region by a layer of gate oxide; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 13

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and separated from said channel and from said n- type region by a layer of gate oxide; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 14

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and extending over said n+ doped region and separated from said channel and from said n- type region and said n+ doped region by a layer of gate oxide; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 15

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and extending over said n+ doped region and separated from said channel and from said n- type region and said n+ doped region by a layer of gate oxide; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 16

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and separated from said channel and from said n- type region and said first and second n+ doped regions by a layer of gate oxide, said floating gate extending over a portion of said first n+ type region and said second n+ type region; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 17

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region disposed at a surface of said semiconductor substrate and surrounded by said n- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above both said channel and said n- type region and separated from said channel and from said n- type region and said first and second n+ doped regions by a layer of gate oxide, said floating gate extending over a portion of said first n+ type region and said second n+ type region; an insulating layer disposed over said floating gate; a conductive region disposed over said insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said n- type region, said fourth potential being positive with respect to said floating gate.

Claim 18

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type source region disposed in said p- type region; a second n+ type drain region disposed in said p- type region; a channel disposed between said first n+ type source region and said second n+ type drain region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel and separated from said channel by an insulator; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 19

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type source region disposed in said p- type region; a second n+ type drain region disposed in said p- type region; a channel disposed between said first n+ type source region and said second n+ type drain region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel and separated from said channel by an insulator; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 20

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel including a region additionally p-doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by an insulator; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 21

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel including a region additionally p-doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by an insulator; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 22

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; an n+ type source region disposed in said p- type region; an n+ type drain region disposed in said p- type region; a channel disposed between said source region and said drain region, said channel including an additionally p doped region having an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel, said floating gate disposed adjacent to at least one edge of each of said drain region and said source region and separated from said semiconductor substrate by a gate oxide under a portion of said floating gate including at least where it is adjacent to an edge of each of said drain region and said source region; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region; means for applying a first positive potential to said drain region with respect to said p- type region to reverse bias said drain region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said drain region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said source region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth positive potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 23

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; an n+ type source region disposed in said p- type region; an n+ type drain region disposed in said p- type region; a channel disposed between said source region and said drain region, said channel including an additionally p doped region having an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed over said channel, said floating gate disposed adjacent to at least one edge of each of said drain region and said source region and separated from said semiconductor substrate by a gate oxide under a portion of said floating gate including at least where it is adjacent to an edge of each of said drain region and said source region; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region; means for applying a first positive potential to said drain region with respect to said p- type region to reverse bias said drain region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said drain region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said source region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth positive potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 24

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 25

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 26

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and extending over a portion of said first and second n+ doped regions and separated from said channel and said first and second n+ doped regions by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 27

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and extending over a portion of said first and second n+ doped regions and separated from said channel and said first and second n+ doped regions by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 28

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and extending over a portion of said first and second n+ doped regions and separated from said channel and said n+ doped regions by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 29

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and extending over a portion of said first and second n+ doped regions and separated from said channel and said n+ doped regions by a layer of gate oxide; an insulating layer disposed over said floating gate; a first conductive region disposed over said insulating layer and capacitively coupled to said floating gate; a tunneling junction disposed between said floating gate and a second conductive region, said tunneling junction including a portion of said insulating layer; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and means for selectively applying a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 30

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by a first insulating layer; a second insulating layer disposed over said floating gate; a first conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and a tunneling junction for causing electrons to tunnel from said floating gate to a second conductive region, in response to selective application of a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 31

An analog memory cell comprising: a semiconductor substrate including a p- type region; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a channel disposed between said first n+ type region and said second n+ type region, said channel additionally p doped to an impurity level in the range of about 1E17/cm 3 to about 2E17/cm 3 ; a floating gate disposed above said channel and separated from said channel by a first insulating layer; a second insulating layer disposed over said floating gate; a first conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for applying a first positive potential to said second n+ type region with respect to said p- type region to reverse bias said second n+ type region with respect to said p- type region, said first positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region, but less than the voltage required to induce avalanche breakdown in a junction formed between said second n+ type region and said p- type region; means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; means for applying a third potential to said first n+ type region with respect to said p- type region, said third potential in the range of about zero to about +2.0 volts relative to said p- type region; and a tunneling junction for causing electrons to tunnel from said floating gate to a second conductive region, in response to selective application of a fourth potential to said second conductive region, said fourth potential being positive with respect to said floating gate.

Claim 32

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a tunneling junction region disposed adjacent to a portion of said floating gate; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 33

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a tunneling junction region disposed adjacent to a portion of said floating gate; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 34

The semiconductor structure according to claim 19 wherein said channel implant region is additionally p doped.

Claim 35

The semiconductor structure according to claim 19 wherein said tunneling junction comprises a second conductive region separated from said floating gate by an insulating material.

Claim 36

The semiconductor structure according to claim 20 wherein said tunneling junction comprises a second conductive region separated from said floating gate by an insulating material.

Claim 37

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 38

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 39

The semiconductor structure according to claim 23 wherein said channel implant region is additionally p doped.

Claim 40

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a tunneling junction region disposed adjacent to a portion of said floating gate; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 41

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a tunneling junction region disposed adjacent to a portion of said floating gate; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 42

The semiconductor structure according to claim 25 wherein said channel implant region is additionally p doped.

Claim 43

The semiconductor structure according to claim 26 wherein said tunneling junction comprises a second conductive region separated from said floating gate by an insulating material.

Claim 44

The semiconductor structure according to claim 25 wherein said tunneling junction comprises a second conductive region separated from said floating gate by an insulating material.

Claim 45

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 46

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region; means for capacitively coupling a positive potential to said floating gate, said positive potential having a magnitude of greater than about +2.5 volts relative to said p- type region; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate.

Claim 47

The analog memory cell according to claim 29 wherein said channel implant region is additionally p doped.

Claim 48

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region.

Claim 49

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region.

Claim 50

The semiconductor structure according to claim 31 including means for simultaneously executing said electron injection and said electron tunneling.

Claim 51

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate to said n+ doped region through said first insulating layer.

Claim 52

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate to said n+ doped region through said first insulating layer.

Claim 53

The semiconductor structure according to claim 33 including means for simultaneously executing said electron injection and said electron tunneling.

Claim 54

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by a first insulating layer; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region.

Claim 55

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by a first insulating layer; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said first insulating layer into said floating gate; means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region.

Claim 56

The analog memory cell according to claim 35 including means for simultaneously executing said electron injection and said electron tunneling.

Claim 57

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, a portion of said floating gate also disposed over said n- type region, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said insulator into said floating gate; means for selectively causing electrons to tunnel electrons from said floating gate to said n+ doped region through said first insulating layer.

Claim 58

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, a portion of said floating gate also disposed over said n- type region, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel implant region through said insulator into said floating gate; means for selectively causing electrons to tunnel electrons from said floating gate to said n+ doped region through said first insulating layer.

Claim 59

The analog memory cell according to claim 37 including means for simultaneously executing said electron injection and said electron tunneling.

Claim 60

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished though selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 61

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a second conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished though selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 62

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 63

A semiconductor structure for long term learning comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 64

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a conductive region separated from said floating gate by a first insulating layer; a second insulating layer disposed over said floating gate; a second conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished though selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 65

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a conductive region separated from said floating gate by a first insulating layer; a second insulating layer disposed over said floating gate; a second conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished though selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 66

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, a portion of said floating gate also disposed over said n- type region, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.

Claim 67

An analog memory cell comprising: a p- type region in a semiconductor substrate; a first n+ type region disposed in said p- type region; a second n+ type region disposed in said p- type region; an n- type region disposed in said p- type region, said n- type region including an n+ doped region surrounded by said n- type region within said p- type region; a floating gate disposed over a channel implant region and separated from said channel implant region by a first insulating layer, a portion of said floating gate also disposed over said n- type region, said channel implant region disposed in said p- type region between said first n+ type region and said second n+ type region, and said channel implant region additionally p doped; a second insulating layer disposed over said floating gate; a conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for simultaneously adding and removing electrons to and from said floating gate, wherein said electron addition is accomplished through selective use of electron injection and said electron removal is accomplished through selective use of electron tunneling.