One-transistor adaptable analog storage element and array

Claim 1

An analog storage array comprising a plurality of cells arranged as a plurality of rows and a plurality of columns, said array disposed on an n-type semiconductor substrate and including: a p-type well disposed in said n-type substrate; a plurality of N-channel MOS transistors disposed in said rows and columns in said p-type well of said n-type semiconductor substrate, a single one of said N-channel MOS transistors comprising each cell, each of said N-channel MOS transistors including a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode; an input line associated with each of said rows, each input line connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated; a bias line associated with each of said rows, each bias line capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated; a tunnel line associated with each of said columns, each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated; a current-sum line associated with each of said columns, each current-sum line connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated; means for forward biasing said p-well with respect to said substrate in order to inject minority electrons into said p-well; and means for selectively raising the drain and source voltages of a selected one of said N-channel floating gate transistors to accelerate the said injected minority electrons enough to enable them to migrate onto the floating gate of said selected one of said N-channel floating gate transistors; and means for simultaneously driving a selected one of said bias lines low while driving a selected one of said tunnel lines high, for causing electron tunneling from the floating gate of the one of the N-channel MOS transistors common to said selected one of said bias lines and said selected one of said tunnel lines.