Patent US6144079A successfully refreshed from Google Patents.
US6144079A
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US
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Semiconductor device and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1996-10-03
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Granted: 2000-11-07
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Expires: 2016-10-03
Abstract
Abstract In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.
Inventors
- 👤 Masayoshi Shirahata
- 👤 Yoshinori Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10P; H10P30/00; H10P30/20; H10P30/21; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/314; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/80; H10D84/82; H10D84/83; H10P30/202; H10P30/204; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
150 words
A semiconductor device, wherein first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, and concentration profiles of one identical conductivity type impurity in sections extending through channel regions of said first and second MIS transistors in a depth direction from said main surface of said semiconductor substrate have peaks at different depths, wherein said first MIS transistor has a first channel region provided with a first impurity layer under said first channel region, and said second MIS transistor has a second channel region provided with a second impurity layer having the same conductivity type as said first impurity layer under said second channel region; and said second MIS transistor has a higher threshold voltage than said first MIS transistor, and said first impurity layer is formed at a position deeper from said main surface than said second impurity layer.
Claim 2
Dependent Claim
150 words
A semiconductor device, wherein first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, and concentration profiles of one identical conductivity type impurity in sections extending through channel regions of said first and second MIS transistors in a depth direction from said main surface of said semiconductor substrate have peaks at different depths, wherein said first MIS transistor has a first channel region provided with a first impurity layer under said first channel region, and said second MIS transistor has a second channel region provided with a second impurity layer having the same conductivity type as said first impurity layer under said second channel region; and said second MIS transistor has a higher threshold voltage than said first MIS transistor, and said first impurity layer is formed at a position deeper from said main surface than said second impurity layer.
Claim 3
Dependent Claim
34 words
The semiconductor device according to claim 1, wherein impurity concentration distributions of said first and second impurity layers are different from each other and depend on thresholds of said first and second MIS transistors.
Claim 4
Dependent Claim
39 words
The semiconductor device according to claim 1, wherein at least one of impurity concentration profiles in sections extending in a depth direction from said main surface through said first and second channel regions has two or more peak values.
Claim 5
Dependent Claim
19 words
The semiconductor device according to claim 1, wherein said first and second impurity layers have different kinds of impurity.
Claim 6
Dependent Claim
88 words
The semiconductor device according to claim 1, wherein a third MIS transistor of the conductivity type same as that of said first and second MIS transistors is further formed at a main surface of a semiconductor substrate; said first, second and third MIS transistors form a sense amplifier, a peripheral circuit and a memory cell, respectively; and impurity concentration profiles in sections extending in a depth direction from said main surface through channel regions of said first, second and third MIS transistors have peaks at different depths, respectively.
Claim 7
Dependent Claim
87 words
The semiconductor device according to claim 1, wherein; said first and second MIS transistors have first and second channel regions, respectively; a first heavily doped layer is provided at a predetermined depth from said main surface under said first channel region; a second heavily doped layer is provided at the substantially same depth as said first heavily doped layer from said main surface under said second channel region; and an impurity layer between said second heavily doped layer and said main surface under said second channel region.
Claim 8
Dependent Claim
36 words
The semiconductor device according to claim 6, wherein said impurity layer formed under said second channel region has a plurality of layers formed at different depths between said second heavily doped layer and said main surface.
Claim 9
Dependent Claim
29 words
The semiconductor device according to claim 6, wherein an impurity contained in said first and second heavily doped layers is different from an impurity contained in said impurity layer.
References Cited (Backward Citations)
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JPH05211331A
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US5641699A
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US5470774A
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US5674763A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |