Fabrication method of a read-only semiconductor memory device

Claim 2

A fabrication method of a semiconductor memory device, said method comprising the steps of: (a) preparing memory cells formed of first MOS transistors and peripheral circuits formed of second MOS transistors on a semiconductor substrate of a first conductivity type, said memory cells being formed in a memory cell area of said substrate, said peripheral circuits being formed in a peripheral circuit area of said substrate; (b) forming a photoresist film on said substrate to cover said memory cell area and said peripheral circuit area; (c) patterning said photoresist film to have windows so that selected ones of said first transistors to be coded are exposed from said photoresist film through said windows, respectively; (d) selectively doping a first dopant of a second conductivity type for coding into said selected ones of said first transistors using said patterned photoresist film as a mask, so that first impurity-doped regions of said second conductivity type being formed in channel areas of said selected ones of said first transistors, respectively, said second conductivity type being opposite in polarity to said first conductivity type; and (e) doping a second dopant of said first conductivity type for threshold adjustment into said first transistors and said second transistors through said patterned photoresist film, so that second impurity-doped regions of said first conductivity type being formed in channel areas of unselected ones of said first transistors and said second transistors, respectively; wherein during said step of (e), said second dopant doped through said selected ones of said first transistors forms third impurity-doped regions of said first conductivity type apart from said channel areas of said selected ones of said first transistors in said substrate, respectively; and wherein said third impurity-doped regions serve to restrain said first dopant doped into said selected ones of said first transistors in said step of (d) from laterally diffusing in said substrate.

Claim 3

The method as claimed in claim 1, wherein said step (d) of selectively doping said first dopant for coding and said step (e) of doping said second dopant for threshold adjustment are carried out by ion-implantation.

Claim 4

The method as claimed in claim 2, wherein first and second transistors have gate electrodes and a gate insulator film, an acceleration energy for carrying out said step (d) of selectively doping said first dopant for coding is set so that said first dopant can pass through said gate electrodes and said gate insulator film of said selected ones of said first transistors into said substrate, respectively; said acceleration energy being set so that said first dopant cannot pass through said patterned photoresist film, said gate electrodes and gate insulator film of said unselected ones of said first transistors and said second transistors into said substrate, respectively.

Claim 5

The method as claimed in claim 2, wherein first transistors and second transistors have gate electrodes and a gate insulator film, an acceleration energy for carrying out said step (e) of doping said second dopant for threshold adjustment is set so that said second dopant can pass through said patterned photoresist film, said gate electrodes and said gate insulator film of said unselected ones of said first transistors and said second transistors into said substrate, respectively; said acceleration energy being set so that said third impurity-doped regions are placed in said substrate apart enough from said first impurity-doped regions not to affect operations of said selected ones of said first transistors, respectively.

Claim 6

The method as claimed in claim 1, further comprising steps of (f), (g) and (h), said steps of (f), (g) and (h) being carried out after said step (d) of selectively doping said first dopant and said step (e) of doping said second dopant; wherein in said step of (f), said patterned photoresist film is removed from said substrate; in said step of (g), an interlayer insulator film is formed on said substrate to cover said memory cell area and said peripheral circuit area; and in said step of (h), said interlayer insulator film is subjected to heat for reflowing said interlayer insulator film.

Claim 7

The method as claimed in claim 2, wherein said step (d) of doping said first dopant for coding is carried out by implanting phosphorus ions into said selected ones of said first transistors at an acceleration energy of 300 to 400 keV with a dose of 1.0 to 5.0×10 13 ions/cm 2 .

Claim 8

The method as claimed in claim 2, wherein said step (e) of doping said second dopant for threshold adjustment is carried out by implanting boron ions into said first transistors and said second transistors at an acceleration energy of 800 to 900 keV with a dose of 1.0 to 2.0×10 13 ions/cm 2 .

Claim 9

The method as claimed in claim 2, wherein said step (d) of doping said first dopant for coding is carried out by implanting phosphorus ions into said selected ones of said first transistors at an acceleration energy of 300 to 400 keV with a dose of 1.0 to 5.0×10 13 ions/cm 2 ; and wherein said step (e) of doping said second dopant for threshold adjustment is carried out by implanting boron ions into said first transistors and said second transistors at an acceleration energy of 800 to 900 keV with a dose of 1.0 to 2.0×10 13 ions/cm 2 .

Claim 10

A fabrication method of a semiconductor memory device, said method comprising the steps of: (a) preparing memory cells formed of first MOS transistors and peripheral circuits formed of second MOS transistors on a semiconductor substrate of a first conductivity type, said memory cells being formed in a memory cell area of said substrate, said peripheral circuits being formed in a peripheral circuit area of said substrate; (b) forming an interlayer insulator film on said substrate to cover said memory cell area and said peripheral circuit area; (c) heating said interlayer insulator film for reflowing said interlayer insulator film; (d) forming a photoresist film on said interlayer insulator film thus reflown to cover said memory cell area and said peripheral circuit area; (e) patterning said photoresist film to have windows so that said windows are placed over selected ones of said first transistors to be coded, respectively; (f) selectively doping a first dopant of a second conductivity type for coding into said selected ones of said first transistors through said interlayer insulator film using said patterned photoresist film as a mask, so that first impurity-doped regions of said second conductivity type being formed in channel areas of said selected ones of said first transistors, respectively, said second conductivity type being opposite in polarity to said first conductivity type; and (g) doping a second dopant of said first conductivity type for threshold adjustment into said first transistors and said second transistors through said patterned photoresist film and said interlayer insulator film, so that second impurity-doped regions of said first conductivity type being formed in channel areas of unselected ones of said first transistors and said second transistors, respectively; wherein during said step of (g), said second dopant doped through said selected ones of said first transistors forms third impurity-doped regions of said first conductivity type apart from said channel areas of said selected ones of said first transistors in said substrate, respectively; and wherein said third impurity-doped regions serve to restrain said first dopant doped into said selected ones of said first transistors in said step of (f) from laterally diffusing in said substrate.

Claim 11

A fabrication method of a semiconductor memory device, said method comprising the steps of: (a) preparing memory cells formed of first MOS transistors and peripheral circuits formed of second MOS transistors on a semiconductor substrate of a first conductivity type, said memory cells being formed in a memory cell area of said substrate, said peripheral circuits being formed in a peripheral circuit area of said substrate; (b) forming an interlayer insulator film on said substrate to cover said memory cell area and said peripheral circuit area; (c) heating said interlayer insulator film for reflowing said interlayer insulator film; (d) forming a photoresist film on said interlayer insulator film thus reflown to cover said memory cell area and said peripheral circuit area; (e) patterning said photoresist film to have windows so that said windows are placed over selected ones of said first transistors to be coded, respectively; (f) selectively doping a first dopant of a second conductivity type for coding into said selected ones of said first transistors through said interlayer insulator film using said patterned photoresist film as a mask, so that first impurity-doped regions of said second conductivity type being formed in channel areas of said selected ones of said first transistors, respectively, said second conductivity type being opposite in polarity to said first conductivity type; and (g) doping a second dopant of said first conductivity type for threshold adjustment into said first transistors and said second transistors through said patterned photoresist film and said interlayer insulator film, so that second impurity-doped regions of said first conductivity type being formed in channel areas of unselected ones of said first transistors and said second transistors, respectively; wherein during said step of (g), said second dopant doped through said selected ones of said first transistors forms third impurity-doped regions of said first conductivity type apart from said channel areas of said selected ones of said first transistors in said substrate, respectively; and wherein said third impurity-doped regions serve to restrain said first dopant doped into said selected ones of said first transistors in said step of (f) from laterally diffusing in said substrate.

Claim 12

The method as claimed in claim 9, wherein said step (f) of selectively doping said first dopant for coding and said step (g) of doping said second dopant for threshold adjustment are carried out by ion-implantation.

Claim 13

The method as claimed in claim 10, wherein first transistors and second transistors have gate electrodes and a gate insulator film, an acceleration energy for carrying out said step (f) of selectively doping said first dopant for coding is set so that said first dopant can pass through said interlayer insulator film, said gate electrodes and said gate insulator film of said selected ones of said first transistors into said substrate, respectively; said acceleration energy being set so that said first dopant cannot pass through said interlayer insulator film, said patterned photoresist film, said gate electrodes and said gate insulator film of said unselected ones of said first transistors and said second transistors into said substrate, respectively.

Claim 14

The method as claimed in claim 10, wherein first transistors and second transistors have gate electrodes and a gate insulator film, an acceleration energy for carrying out said step (g) of doping said second dopant for threshold adjustment is set so that said second dopant can pass through said interlayer insulator film, said patterned photoresist film, said gate electrodes and said gate insulator film of said unselected ones of said first transistors and said second transistors into said substrate, respectively; said acceleration energy being set so that said third impurity-doped regions are placed in said substrate apart enough from said first impurity-doped regions not to affect operations of said selected ones of said first transistors, respectively.

Claim 15

The method as claimed in claim 9, further comprising steps of (h) and (i), said steps of (h) and (i) being carried out between said step (b) of forming said interlayer insulator film and said step (c) of heating said interlayer insulator film for reflowing; wherein in said step of (h), contact holes are formed in said interlayer insulator film; and in said step of (i), contact regions are formed in said substrate at positions corresponding to said contact holes, said contact regions being electrically interconnected through said corresponding contact holes with a conductive film to be formed on said interlayer insulator film.

Claim 16

The method as claimed in claim 10, wherein said step (f) of doping said first dopant for coding is carried out by implanting phosphorus ions into said selected ones of said first transistors at an acceleration energy of 1.0 to 1.1 MeV with a dose of 1.0 to 5.0×10 13 ions/cm 2 .

Claim 17

The method as claimed in claim 10, wherein said step (g) of doping said second dopant for threshold adjustment is carried out by implanting boron ions into said first transistors and said second transistors at an acceleration energy of 2.0 to 2.1 MeV with a dose of 1.0 to 5.0×10 13 ions/cm 2 .

Claim 18

The method as claimed in claim 10, wherein said step (f) of doping said first dopant for coding is carried out by implanting phosphorus ions into said selected ones of said first transistors at an acceleration energy of 1.0 to 1.1 MeV with a dose of 1.0 to 5.0×10 13 ions/cm 2 ; and wherein said step (g) of doping said second dopant for threshold adjustment is carried out by implanting boron ions into said first transistors and said second transistors at an acceleration energy of 2.0 to 2.1 MeV with a dose of 1.0 to 5.0×10 13 ions/cm 2 .