Patent US6141248A successfully refreshed from Google Patents.
US6141248A
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DRAM and SRAM memory cells with repressed memory
Assignee: Micron Technology Inc
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Filing: 1999-07-29
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Granted: 2000-10-31
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Expires: 2019-07-29
Abstract
Abstract The transfer device of a typical DRAM cell is replaced with a transistor having an additional gate. The unique cell can be accessed as a typical DRAM cell by reading from or writing to a storage capacitor or as a nonvolatile memory by storing charges on the additional gate. Thus, a DRAM cell having a nonvolatile memory component within its cell is formed in a simple and cost effective manner. Transistors in a typical SRAM cell are also replaced by the transistors with the additional gate to form a SRAM cell having a nonvolatile component built within its cell.
Inventors
- 👤 Leonard Forbes
- 👤 Alan R. Reinberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:09
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 94
Claim 1
Independent Claim
86 words
A memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 2
Dependent Claim
86 words
A memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 3
Dependent Claim
23 words
The memory cell of claim 1 wherein said first source of information is a storage capacitor of a dynamic random access memory device.
Claim 4
Dependent Claim
27 words
The memory cell of claim 2 wherein said transistor comprises a control gate and an additional gate and said second source of information is said additional gate.
Claim 5
Dependent Claim
14 words
The memory cell of claim 3 wherein said additional gate is a floating gate.
Claim 6
Dependent Claim
14 words
The memory cell of claim 4 wherein said floating gate is comprised of polysilicon.
Claim 7
Dependent Claim
38 words
The memory cell of claim 3 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from a source region of said transistor to said additional gate.
Claim 8
Dependent Claim
38 words
The memory cell of claim 3 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from said additional gate to a source region of said transistor.
Claim 9
Dependent Claim
19 words
The memory cell of claim 1 wherein said first source of information is a static random access memory device.
Claim 10
Dependent Claim
22 words
The memory cell of claim 1 wherein said first source of information is a silicon oxide nitride oxide silicon (SONOS) memory device.
Claim 11
Dependent Claim
153 words
A memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 12
Dependent Claim
153 words
A memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 13
Dependent Claim
22 words
The memory cell of claim 10 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 14
Dependent Claim
14 words
The memory cell of claim 11 wherein said floating gate is comprised of polysilicon.
Claim 15
Dependent Claim
26 words
The memory cell of claim 11 wherein said second charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 16
Dependent Claim
26 words
The memory cell of claim 11 wherein said second charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 17
Dependent Claim
19 words
The memory cell of claim 10 wherein said first mode of operation is a volatile memory mode of operation.
Claim 18
Dependent Claim
41 words
The memory cell of claim 15 wherein said first charge is read from said storage capacitor by applying a voltage in excess of a threshold voltage of said transistor to said control gate and sensing a potential of said bit line.
Claim 19
Dependent Claim
19 words
The memory cell of claim 10 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 20
Dependent Claim
41 words
The memory cell of claim 17 wherein said second charge is read from said floating gate by applying a voltage approximately equal to a threshold voltage of said transistor to said control gate and sensing a response time of said transistor.
Claim 21
Dependent Claim
227 words
A memory cell, comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 22
Dependent Claim
227 words
A memory cell, comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 23
Dependent Claim
22 words
The memory cell of claim 19 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 24
Dependent Claim
14 words
The memory cell of claim 20 wherein said floating gate is comprised of polysilicon.
Claim 25
Dependent Claim
25 words
The memory cell of claim 20 wherein said charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 26
Dependent Claim
25 words
The memory cell of claim 20 wherein said charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 27
Dependent Claim
19 words
The memory cell of claim 19 wherein said first mode of operation is a volatile memory mode of operation.
Claim 28
Dependent Claim
19 words
The memory cell of claim 19 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 29
Dependent Claim
105 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 30
Dependent Claim
105 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 31
Dependent Claim
23 words
The memory circuit of claim 26 wherein said first source of information is a storage capacitor of a dynamic random access memory device.
Claim 32
Dependent Claim
27 words
The memory circuit of claim 27 wherein said transistor comprises a control gate and an additional gate and said second source of information is said additional gate.
Claim 33
Dependent Claim
14 words
The memory circuit of claim 28 wherein said additional gate is a floating gate.
Claim 34
Dependent Claim
14 words
The memory circuit of claim 29 wherein said floating gate is comprised of polysilicon.
Claim 35
Dependent Claim
38 words
The memory circuit of claim 28 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from a source region of said transistor to said additional gate.
Claim 36
Dependent Claim
38 words
The memory circuit of claim 28 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from said additional gate to a source region of said transistor.
Claim 37
Dependent Claim
19 words
The memory circuit of claim 26 wherein said first source of information is a static random access memory device.
Claim 38
Dependent Claim
22 words
The memory circuit of claim 26 wherein said first source of information is a silicon oxide nitride oxide silicon (SONOS) memory device.
Claim 39
Dependent Claim
172 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 40
Dependent Claim
172 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 41
Dependent Claim
22 words
The memory circuit of claim 35 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 42
Dependent Claim
14 words
The memory circuit of claim 36 wherein said floating gate is comprised of polysilicon.
Claim 43
Dependent Claim
26 words
The memory circuit of claim 36 wherein said second charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 44
Dependent Claim
26 words
The memory circuit of claim 36 wherein said second charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 45
Dependent Claim
19 words
The memory circuit of claim 35 wherein said first mode of operation is a volatile memory mode of operation.
Claim 46
Dependent Claim
41 words
The memory circuit of claim 40 wherein said first charge is read from said storage capacitor by applying a voltage in excess of a threshold voltage of said transistor to said control gate and sensing a potential of said bit line.
Claim 47
Dependent Claim
19 words
The memory circuit of claim 35 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 48
Dependent Claim
41 words
The memory circuit of claim 42 wherein said second charge is read from said floating gate by applying a voltage approximately equal to a threshold voltage of said transistor to said control gate and sensing a response time of said transistor.
Claim 49
Dependent Claim
247 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 50
Dependent Claim
247 words
A memory circuit comprising: a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 51
Dependent Claim
22 words
The memory circuit of claim 44 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 52
Dependent Claim
14 words
The memory circuit of claim 45 wherein said floating gate is comprised of polysilicon.
Claim 53
Dependent Claim
25 words
The memory circuit of claim 45 wherein said charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 54
Dependent Claim
25 words
The memory circuit of claim 45 wherein said charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 55
Dependent Claim
19 words
The memory circuit of claim 45 wherein said first mode of operation is a volatile memory mode of operation.
Claim 56
Dependent Claim
19 words
The memory circuit of claim 44 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 57
Dependent Claim
118 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 58
Dependent Claim
118 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
Claim 59
Dependent Claim
21 words
The system claim 51 wherein said first source of information is a storage capacitor of a dynamic random access memory device.
Claim 60
Dependent Claim
26 words
The system of claim 52 wherein said transistor comprises a control gate and an additional gate and said second source of information is said additional gate.
Claim 61
Dependent Claim
13 words
The system of claim 53 wherein said additional gate is a floating gate.
Claim 62
Dependent Claim
13 words
The system of claim 54 wherein said floating gate is comprised of polysilicon.
Claim 63
Dependent Claim
37 words
The system of claim 53 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from a source region of said transistor to said additional gate.
Claim 64
Dependent Claim
37 words
The system of claim 53 wherein said second information is a charge representing a data value that is stored on said additional gate by tunneling electrons from said additional gate to a source region of said transistor.
Claim 65
Dependent Claim
18 words
The system of claim 51 wherein said first source of information is a static random access memory device.
Claim 66
Dependent Claim
21 words
The system of claim 51 wherein said first source of information is a silicon oxide nitride oxide silicon (SONOS) memory device.
Claim 67
Dependent Claim
185 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 68
Dependent Claim
185 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge.
Claim 69
Dependent Claim
21 words
The system of claim 60 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 70
Dependent Claim
13 words
The system of claim 61 wherein said floating gate is comprised of polysilicon.
Claim 71
Dependent Claim
25 words
The system of claim 61 wherein said second charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 72
Dependent Claim
25 words
The system of claim 61 wherein said second charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 73
Dependent Claim
18 words
The system of claim 60 wherein said first mode of operation is a volatile memory mode of operation.
Claim 74
Dependent Claim
40 words
The system of claim 65 wherein said first charge is read from said storage capacitor by applying a voltage in excess of a threshold voltage of said transistor to said control gate and sensing a potential of said bit line.
Claim 75
Dependent Claim
18 words
The system of claim 60 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 76
Dependent Claim
40 words
The system of claim 67 wherein said second charge is read from said floating gate by applying a voltage approximately equal to a threshold voltage of said transistor to said control gate and sensing a response time of said transistor.
Claim 77
Dependent Claim
259 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and control circuitry for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 78
Dependent Claim
259 words
A processor-based system, comprising: a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising: first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and control circuitry for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes.
Claim 79
Dependent Claim
21 words
The system of claim 69 wherein said first gate is a control gate and said second gate is a floating gate.
Claim 80
Dependent Claim
13 words
The system of claim 70 wherein said floating gate is comprised of polysilicon.
Claim 81
Dependent Claim
24 words
The system of claim 70 wherein said charge is stored on said floating gate by tunneling electrons from said source to said floating gate.
Claim 82
Dependent Claim
24 words
The system of claim 70 wherein said charge is stored on said floating gate by tunneling electrons from said floating gate to said source.
Claim 83
Dependent Claim
18 words
The system of claim 69 wherein said first mode of operation is a volatile memory mode of operation.
Claim 84
Dependent Claim
18 words
The system of claim 69 wherein said second mode of operation is a nonvolatile memory mode of operation.
Claim 85
Independent Claim
78 words
A method of reading information from a memory cell comprising at least one transistor, said method comprising the steps of: reading first information from a first source of stored information in a first volatile memory mode of operation; and reading second information from a second source of stored information in a second nonvolatile mode of operation, wherein said first information is read without affecting said second information and said second information is read without affecting said first information.
Claim 86
Independent Claim
78 words
A method of reading information from a memory cell comprising at least one transistor, said method comprising the steps of: reading first information from a first source of stored information in a first volatile memory mode of operation; and reading second information from a second source of stored information in a second nonvolatile mode of operation, wherein said first information is read without affecting said second information and said second information is read without affecting said first information.
Claim 87
Dependent Claim
18 words
The method of claim 76 wherein the first mode of operation is a volatile memory mode of operation.
Claim 88
Dependent Claim
18 words
The method of claim 77 wherein the second mode of operation is a nonvolatile memory mode of operation.
Claim 89
Independent Claim
112 words
A method of reading information from a memory cell comprising a transistor having a control gate and a floating gate and a storage capacitor connected to said transistor, said method comprising the steps of: reading a data value from the capacitor in a first mode of operation of the cell; and reading a data value from the floating gate in a second mode of operation of the cell, wherein the reading of a data value from the capacitor does not affect contents of the data value on the floating gate and the reading of a data value from the floating gate does not affect contents of the data value on the capacitor.
Claim 90
Independent Claim
112 words
A method of reading information from a memory cell comprising a transistor having a control gate and a floating gate and a storage capacitor connected to said transistor, said method comprising the steps of: reading a data value from the capacitor in a first mode of operation of the cell; and reading a data value from the floating gate in a second mode of operation of the cell, wherein the reading of a data value from the capacitor does not affect contents of the data value on the floating gate and the reading of a data value from the floating gate does not affect contents of the data value on the capacitor.
Claim 91
Dependent Claim
18 words
The method of claim 79 wherein the first mode of operation is a volatile memory mode of operation.
Claim 92
Dependent Claim
44 words
The method of claim 80 wherein said step of reading a data value from the capacitor comprises: applying a voltage in excess of a threshold voltage of the transistor to its control gate; and sensing a potential of a charge stored in said capacitor.
Claim 93
Dependent Claim
18 words
The method of claim 80 wherein the second mode of operation is a nonvolatile memory mode of operation.
Claim 94
Dependent Claim
46 words
The method of claim 82 wherein said step of reading a data value from the floating gate comprises: applying a voltage approximately equal to a threshold voltage of the transistor to its control gate; and sensing a response time of a sense amplifier sensing the transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |