US5870327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mixed mode RAM/ROM cell using antifuses
Assignee: Xilinx Inc
•
Filing: 1997-11-03
•
Granted: 1999-02-09
•
Expires: 2017-11-03
Abstract
Abstract A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.
Inventors
- 👤 Daniel Gitlin
- 👤 Dennis L. Segers
- 👤 Michael J. Hart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
123 words
A memory device comprising: a latch having a first and a second inverter, each inverter having an input and an output terminal, wherein the input terminal of said first inverter is coupled to the output terminal of said second inverter, thereby forming a first node, and wherein the input terminal of said second inverter is coupled to the output terminal of said first inverter, thereby forming a second node; an access transistor coupled to said first node; one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to one of said first node and said second node; and programming circuitry coupled to said second terminal of said antifuse.
Claim 2
Dependent Claim
123 words
A memory device comprising: a latch having a first and a second inverter, each inverter having an input and an output terminal, wherein the input terminal of said first inverter is coupled to the output terminal of said second inverter, thereby forming a first node, and wherein the input terminal of said second inverter is coupled to the output terminal of said first inverter, thereby forming a second node; an access transistor coupled to said first node; one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to one of said first node and said second node; and programming circuitry coupled to said second terminal of said antifuse.
Claim 3
Dependent Claim
49 words
A memory device comprising: a volatile memory cell; one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to said volatile memory cell; and programming circuitry coupled to said second terminal of said antifuse.
Claim 4
Dependent Claim
49 words
A memory device comprising: a volatile memory cell; one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to said volatile memory cell; and programming circuitry coupled to said second terminal of said antifuse.
Claim 5
Independent Claim
154 words
A device including a distributed group of memory cells, said device comprising: a plurality of memory cells, wherein at least one memory cell includes: a latch including a first and a second inverter, each inverter having an input and an output terminal, wherein the input terminal of said first inverter is coupled to the output terminal of said second inverter, thereby forming a first node, and wherein the input terminal of said second inverter is coupled to the output terminal of said first inverter, thereby forming a second node; an access transistor coupled to said first node; one and only one antifuse in each memory cell, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to one of said first node and said second node; addressing circuitry coupled to said access transistor; and programming circuitry coupled to said second terminal of said antifuse.
Claim 6
Independent Claim
154 words
A device including a distributed group of memory cells, said device comprising: a plurality of memory cells, wherein at least one memory cell includes: a latch including a first and a second inverter, each inverter having an input and an output terminal, wherein the input terminal of said first inverter is coupled to the output terminal of said second inverter, thereby forming a first node, and wherein the input terminal of said second inverter is coupled to the output terminal of said first inverter, thereby forming a second node; an access transistor coupled to said first node; one and only one antifuse in each memory cell, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to one of said first node and said second node; addressing circuitry coupled to said access transistor; and programming circuitry coupled to said second terminal of said antifuse.
Claim 7
Independent Claim
86 words
A device including a distributed group of memory cells, said device comprising: a plurality of memory cells, wherein at least one memory cell includes: a volatile memory cell including at least one access transistor; and one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to said volatile memory cell; addressing circuitry coupled to said at least one access transistor; and programming circuitry coupled to said second terminal of said antifuse.
Claim 8
Independent Claim
86 words
A device including a distributed group of memory cells, said device comprising: a plurality of memory cells, wherein at least one memory cell includes: a volatile memory cell including at least one access transistor; and one and only one antifuse, wherein said antifuse has a first terminal and a second terminal, wherein said first terminal of said antifuse is coupled to said volatile memory cell; addressing circuitry coupled to said at least one access transistor; and programming circuitry coupled to said second terminal of said antifuse.
Claim 9
Independent Claim
76 words
A method of programming a plurality of memory cells in a memory cell array, wherein each memory cell comprises a volatile memory cell and one and only one antifuse, wherein said antifuse is coupled to said volatile memory cell at a node, wherein said programming method comprises: (a) latching a plurality of configuration bits into said volatile memory cells; (b) providing a programming voltage pulse to said antifuses; and (c) writing logic zeros to said nodes.
Claim 10
Independent Claim
76 words
A method of programming a plurality of memory cells in a memory cell array, wherein each memory cell comprises a volatile memory cell and one and only one antifuse, wherein said antifuse is coupled to said volatile memory cell at a node, wherein said programming method comprises: (a) latching a plurality of configuration bits into said volatile memory cells; (b) providing a programming voltage pulse to said antifuses; and (c) writing logic zeros to said nodes.
References Cited (Backward Citations)
USRE34363E
Cited
US4750155A
Cited
US5581505A
Cited
US5110754A
Cited
US5200652A
Cited
US5475253A
Cited
US5486707A
Cited
US5426614A
Cited
US5495436A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |