Patent US6140688A successfully refreshed from Google Patents.
US6140688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with self-aligned metal-containing gate
Assignee: GlobalFoundries Inc
•
Filing: 1998-09-21
•
Granted: 2000-10-31
•
Expires: 2018-09-21
Abstract
Abstract A semiconductor device is provided and formed using self-aligned metal-containing gates within a metal-oxide semiconductor (MOS) process. After forming junction regions within a semiconductor substrate, the gate conductor, or junction implant alignment structure, is at least partially removed to form a trench within a dielectric formed above the substrate. Upper surfaces of the transistor, except the upper surface of the gate conductor, are thereby protected by the dielectric. A metal-containing material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The metal material can be formed either as a single layer or as multiple metal and/or dielectric layers interposed throughout the as-filled trench. The metal-filled trench formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
Inventors
- 👤 Mark I. Gardner
- 👤 Sey-Ping Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:22
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/48; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0411; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/031; H10D64/035; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/014; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/83135; H10B41/41; H10D64/017
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
39 words
A transistor, comprising a multi-layered gate conductor dielectrically spaced above a semiconductor substrate, wherein at least one layer of the multi-layered gate conductor comprises metal, and wherein the a layer of polycrystalline silicon is formed upon the metal layer.
Claim 2
Dependent Claim
39 words
A transistor, comprising a multi-layered gate conductor dielectrically spaced above a semiconductor substrate, wherein at least one layer of the multi-layered gate conductor comprises metal, and wherein the a layer of polycrystalline silicon is formed upon the metal layer.
Claim 3
Dependent Claim
24 words
The transistor as recited in claim 1, further comprising a pair of dielectric spacers configured adjacent opposed sidewall surfaces of the multi-layered gate conductor.
Claim 4
Dependent Claim
40 words
The transistor as recited in claim 1, wherein the multi-layered gate conductor comprises a layer of metal or polycrystalline silicon formed upon a dielectric comprising a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride.
Claim 5
Dependent Claim
39 words
The transistor as recited in claim 1, wherein the multi-layered conductor includes a dielectric comprising a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride formed upon a layer of polycrystalline silicon or metal.
Claim 6
Dependent Claim
28 words
The transistor as recited in claim 1, wherein the multi-layered conductor includes a layer of metal formed upon a layer of polycrystalline silicon or another layer of metal.
Claim 7
Dependent Claim
12 words
The transistor as recited in claim 1, wherein said metal comprises copper.
Claim 8
Dependent Claim
25 words
The transistor as recited in claim 1, wherein said multi-layered gate conductor is separated from said semiconductor substrate by a gate dielectric comprising silicon nitride.
Claim 9
Dependent Claim
12 words
The transistor as recited in claim 1, wherein said metal comprises aluminum.
Claim 10
Dependent Claim
35 words
A transistor, comprising: a pair of junctions within a semiconductor substrate separated from each other by a channel; and a metal-based gate conductor configured within a trench existing in lateral alignment directly above said channel.
Claim 11
Dependent Claim
35 words
A transistor, comprising: a pair of junctions within a semiconductor substrate separated from each other by a channel; and a metal-based gate conductor configured within a trench existing in lateral alignment directly above said channel.
Claim 12
Dependent Claim
25 words
The transistor as recited in claim 9, further comprising a dielectric existing above the pair of junctions and terminating as a sidewall of the trench.
Claim 13
Dependent Claim
25 words
The transistor as recited in claim 10, wherein an upper surface of the dielectric is coplanar with an upper surface of the metal-based gate conductor.
Claim 14
Dependent Claim
28 words
The transistor as recited in claim 10, wherein said dielectric includes a spacer, and wherein a substantially vertical surface of said spacer forms said sidewall of said trench.
Claim 15
Dependent Claim
23 words
The transistor as recited in claim 9, wherein the metal-based gate conductor comprises at least two layers, of which one layer comprises metal.
Claim 16
Dependent Claim
21 words
The transistor as recited in claim 9, wherein the metal-based gate conductor comprises a contiguous layer of metal or metal alloy.
Claim 17
Dependent Claim
191 words
An integrated circuit, comprising: a first active region of a semiconductor substrate separated from a second active region of said substrate by an isolation region; a first gate structure comprising a first gate region interposed between a pair of opposed first sidewall surfaces, arranged above said first active region; a second gate structure comprising a second gate region interposed between a pair of opposed second sidewall surfaces, arranged above said second active region, wherein an upper surface of said second gate structure is at a level commensurate with an upper surface of said first gate structure; a first gate dielectric arranged between said first active region and said first gate structure; a second gate dielectric arranged between said second active region and said second gate structure; and dielectric regions arranged above said first active region and said second active region, and adjacent to lateral surfaces of said first gate structure and said second gate structure, such that upper surfaces of said dielectric regions are at a level commensurate with said upper surface of said first gate structure, and wherein the dielectric regions substantially cover the upper surface of the semiconductor substrate.
Claim 18
Dependent Claim
191 words
An integrated circuit, comprising: a first active region of a semiconductor substrate separated from a second active region of said substrate by an isolation region; a first gate structure comprising a first gate region interposed between a pair of opposed first sidewall surfaces, arranged above said first active region; a second gate structure comprising a second gate region interposed between a pair of opposed second sidewall surfaces, arranged above said second active region, wherein an upper surface of said second gate structure is at a level commensurate with an upper surface of said first gate structure; a first gate dielectric arranged between said first active region and said first gate structure; a second gate dielectric arranged between said second active region and said second gate structure; and dielectric regions arranged above said first active region and said second active region, and adjacent to lateral surfaces of said first gate structure and said second gate structure, such that upper surfaces of said dielectric regions are at a level commensurate with said upper surface of said first gate structure, and wherein the dielectric regions substantially cover the upper surface of the semiconductor substrate.
Claim 19
Dependent Claim
49 words
The integrated circuit as recited in claim 15, wherein said first gate structure further comprises a pair of first dielectric spacers adjacent to said opposed first sidewall surfaces, and wherein said second gate structure further comprises a pair of second dielectric spacers adjacent to said opposed second sidewall surfaces.
Claim 20
Dependent Claim
15 words
The integrated circuit as recited in claim 15, wherein said first gate region comprises silicon.
Claim 21
Dependent Claim
17 words
The integrated circuit as recited in claim 17, wherein said second gate region comprises a metal region.
Claim 22
Dependent Claim
18 words
The integrated circuit as recited in claim 15, wherein said first gate region comprises a first metal layer.
Claim 23
Dependent Claim
39 words
The integrated circuit as recited in claim 19, wherein said second gate region comprises a second metal layer, and wherein a work function of said second metal layer is different than a work function of said first metal layer.
References Cited (Backward Citations)
US3936860A
Cited
US5932919A
Cited
US5894160A
Cited
US5780891A
Cited
US5932920A
Cited
US5783850A
Cited
US5616948A
Cited
US5744845A
Cited
US5828130A
Cited
US5952701A
Cited
US5962904A
Cited
US5940698A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |