US6136713A
Expired / Lapsed
US
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Method for forming a shallow trench isolation structure
Assignee: United Microelectronics Corp
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Filing: 1998-10-02
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Granted: 2000-10-24
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Expires: 2018-10-02
Abstract
Abstract A method for forming a shallow trench isolation (STI) structure adds an etching back process to a conventional method which only uses a chemical mechanical process (CMP) process to accomplish the STI structure. In the method of the invention, the CMP process preliminarily planarizes a substrate to remove an insulation layer above the trench and uses the etching back process to accomplish the STI structure.
Inventors
- 👤 Coming Chen
- 👤 Jenn Tsao
- 👤 Water Lur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:57
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
115 words
A method for forming a shallow trench isolation (STI) structure, the method comprising: forming a masking layer over a semiconductor substrate, wherein the masking layer is patterned to expose a portion of the substrate; forming a trench in the substrate at the exposed region; forming an insulating layer over the substrate, wherein the trench is at least filled; performing a chemical mechanical polishing (CMP) process to preliminarily polish the insulating layer so that the masking layer remains unexposed; and etching the insulating layer which is above the level of the upper surface of the masking layer so that the masking layer is exposed, wherein the remaining insulating layer within the trench forms the STI structure.
Claim 2
Independent Claim
115 words
A method for forming a shallow trench isolation (STI) structure, the method comprising: forming a masking layer over a semiconductor substrate, wherein the masking layer is patterned to expose a portion of the substrate; forming a trench in the substrate at the exposed region; forming an insulating layer over the substrate, wherein the trench is at least filled; performing a chemical mechanical polishing (CMP) process to preliminarily polish the insulating layer so that the masking layer remains unexposed; and etching the insulating layer which is above the level of the upper surface of the masking layer so that the masking layer is exposed, wherein the remaining insulating layer within the trench forms the STI structure.
Claim 3
Dependent Claim
12 words
The method of claim 1, wherein the masking layer comprises silicon nitride.
Claim 4
Dependent Claim
11 words
The method of claim 1, wherein the insulating layer comprises oxide.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein the step of performing the CMP process comprises a condition of a fixed period of performing time.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein the step of performing the CMP process comprises a condition of setting a fixed polishing ending point.
Claim 7
Dependent Claim
18 words
The method of claim 1, wherein the step of etching the insulating layer comprises an etching back process.
Claim 8
Dependent Claim
15 words
The method of claim 6, wherein the etching back process comprises a dry etching process.
Claim 9
Dependent Claim
16 words
The method of claim 7, wherein the dry etching process comprises a reactive ion etching (RIE).
Claim 10
Independent Claim
110 words
A method for forming a shallow trench isolation (STI) structure, the method comprising: forming a masking layer over a semiconductor substrate, wherein the masking layer is patterned to expose a plurality of isolation regions; forming a plurality of trenches in the substrate at the isolation regions; forming an insulating layer over the substrate; performing a chemical mechanical polishing (CMP) process to preliminarily polish the insulating layer so that the masking layer remains unexposed; and etching the insulating layer, which is above the level of the upper surface of the masking layer so that the masking layer is exposed, wherein the remaining insulating layer within the trenches forms the STI structure.
Claim 11
Independent Claim
110 words
A method for forming a shallow trench isolation (STI) structure, the method comprising: forming a masking layer over a semiconductor substrate, wherein the masking layer is patterned to expose a plurality of isolation regions; forming a plurality of trenches in the substrate at the isolation regions; forming an insulating layer over the substrate; performing a chemical mechanical polishing (CMP) process to preliminarily polish the insulating layer so that the masking layer remains unexposed; and etching the insulating layer, which is above the level of the upper surface of the masking layer so that the masking layer is exposed, wherein the remaining insulating layer within the trenches forms the STI structure.
Claim 12
Dependent Claim
12 words
The method of claim 9, wherein the masking layer comprises silicon nitride.
Claim 13
Dependent Claim
11 words
The method of claim 9, wherein the insulating layer comprises oxide.
Claim 14
Dependent Claim
23 words
The method of claim 9, wherein the step of performing the CMP process comprises a condition of a fixed period of performing time.
Claim 15
Dependent Claim
23 words
The method of claim 9, wherein the step of performing the CMP process comprises a condition of setting a fixed polishing ending point.
Claim 16
Dependent Claim
18 words
The method of claim 9, wherein the step of etching the insulating layer comprises an etching back process.
Claim 17
Dependent Claim
15 words
The method of claim 14, wherein the etching back process comprises a dry etching process.
Claim 18
Dependent Claim
16 words
The method of claim 15 wherein the dry etching process comprises a reactive ion etching (RIE).
Claim 19
Independent Claim
121 words
A method for filling an opening with material, in which the opening is formed in a semiconductor substrate having a first layer on it, the method comprising: forming a dielectric layer over the substrate, wherein the opening is at least filled and a region abutting the opening is also covered; performing a chemical mechanical polishing (CMP) process to preliminarily polish the dielectric layer so that the first layer, which is under the dielectric layer, is not exposed; and performing an etching back process to remove the dielectric layer other than the opening so that the first layer is exposed and the remaining dielectric layer within the opening is simultaneously planarized to have the same height as that of the first layer.
Claim 20
Independent Claim
121 words
A method for filling an opening with material, in which the opening is formed in a semiconductor substrate having a first layer on it, the method comprising: forming a dielectric layer over the substrate, wherein the opening is at least filled and a region abutting the opening is also covered; performing a chemical mechanical polishing (CMP) process to preliminarily polish the dielectric layer so that the first layer, which is under the dielectric layer, is not exposed; and performing an etching back process to remove the dielectric layer other than the opening so that the first layer is exposed and the remaining dielectric layer within the opening is simultaneously planarized to have the same height as that of the first layer.
Claim 21
Dependent Claim
12 words
The method of claim 17, wherein the first layer comprises silicon nitride.
Claim 22
Dependent Claim
11 words
The method of claim 17, wherein the dielectric layer comprises oxide.
Claim 23
Dependent Claim
17 words
The method of claim 17, wherein the etching back process comprises a reactive ion etching (RIE) process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |