US5094972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Means of planarizing integrated circuits with fully recessed isolation dielectric
Assignee: National Semiconductor Corp
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Filing: 1990-06-14
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Granted: 1992-03-10
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Expires: 2010-06-14
Abstract
Abstract An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
Inventors
- 👤 John M. Pierce
- 👤 Sung T. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:49
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P95/00; H10P95/06; H10P95/062; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; Y; Y10; Y10S; Y10S438/00; Y10S438/959
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
185 words
A method of fabricating an integrated circuit device upon a semiconductor wafer, comprising the steps of: (a) forming a stop layer upon the surface of said semiconductor wafer, (b) forming openings of varying widths through said stop layer, (c) forming a plurality of isolation wells of varying widths including isolation wells which re relatively narrow and isolation wells which are relatively wide with respect to said relatively narrow isolation wells in said semiconductor wafer blow said openings, (d) forming a dielectric layer over the surface of said integrated circuit device including over said relatively wide isolation wells, (e) mechanical planarizing of said dielectric layer to substantially the level of said stop layer by means of a semirigid pad applied directly to said dielectric material over said relatively wide isolation wells, the rigidity of said semirigid pad being sufficient to bridge said relatively wide isolation wells to limit removal of said dielectric material from within said relatively wide isolation wells below the level of said stop layer, and (f) said openings of said relatively wide wells having a dimension substantially equal to one millimeter or more.
Claim 2
Independent Claim
185 words
A method of fabricating an integrated circuit device upon a semiconductor wafer, comprising the steps of: (a) forming a stop layer upon the surface of said semiconductor wafer, (b) forming openings of varying widths through said stop layer, (c) forming a plurality of isolation wells of varying widths including isolation wells which re relatively narrow and isolation wells which are relatively wide with respect to said relatively narrow isolation wells in said semiconductor wafer blow said openings, (d) forming a dielectric layer over the surface of said integrated circuit device including over said relatively wide isolation wells, (e) mechanical planarizing of said dielectric layer to substantially the level of said stop layer by means of a semirigid pad applied directly to said dielectric material over said relatively wide isolation wells, the rigidity of said semirigid pad being sufficient to bridge said relatively wide isolation wells to limit removal of said dielectric material from within said relatively wide isolation wells below the level of said stop layer, and (f) said openings of said relatively wide wells having a dimension substantially equal to one millimeter or more.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein step (a) is preceded by the step of forming a PAD oxide layer upon the surface of said semiconductor wafer.
Claim 4
Dependent Claim
12 words
The method of claim 1, wherein said stop layer comprises silicon nitride.
Claim 5
Dependent Claim
26 words
The method of claim 1, wherein step (c) is followed by the step of performing a thin field oxidation upon the exposed surfaces of said wells.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein step (c) is followed by the step of performing implants into the walls of said wells.
Claim 7
Dependent Claim
18 words
The method of claim 1, wherein step (d) comprises substantially covering said stop layer with said dielectric layer.
Claim 8
Dependent Claim
18 words
The method of claim 1, wherein step (e) comprises chemical mechanical polishing by means of mechanical polishing means.
Claim 9
Dependent Claim
26 words
The method of claim 7, wherein said polishing comprises self-stopping polishing for slowing said mechanical polishing means when said mechanical polishing means encounters said stop layer.
Claim 10
Dependent Claim
22 words
The method of claim 1, further comprising the step of removing said stop layer to expose active regions of said semiconductor wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |