US6127232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions
Assignee: Texas Instruments Inc
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Filing: 1999-06-24
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Granted: 2000-10-03
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Expires: 2019-06-24
Abstract
Abstract A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.
Inventors
- 👤 Amitava Chatterjee
- 👤 Richard A. Chapman
- 👤 Syed Suhail Murtaza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/027; H10D30/0275; H10D30/0278; H10D30/60; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/017; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0135; H10D84/014; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17; H10D84/8311; H10D84/83135; Y; Y10; Y10S; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of gate oxide on the doped epitaxial silicon layer; forming a disposable gate on the gate oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the gate oxide; removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the gate oxide layer to expose the first layer of doped epitaxial silicon, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; and depositing a permanent gate material in the recess and extending into the opposing laterally extended notches.
Claim 2
Independent Claim
170 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of gate oxide on the doped epitaxial silicon layer; forming a disposable gate on the gate oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the gate oxide; removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the gate oxide layer to expose the first layer of doped epitaxial silicon, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; and depositing a permanent gate material in the recess and extending into the opposing laterally extended notches.
Claim 3
Independent Claim
217 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of gate oxide on the doped epitaxial silicon layer; forming a disposable gate on the gate oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the gate oxide; removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the gate oxide layer to expose the first epitaxial silicon substrate; forming an oxide with the first epitaxial silicon substrate layer, the oxide extending downwardly into the first epitaxial silicon substrate layer; removing the oxide to define a groove in the first epitaxial silicon substrate layer, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; forming a gate oxide in the recess on the exposed first epitaxial silicon substrate layer; and depositing a permanent gate material in the recess extending into the opposing laterally extended notches.
Claim 4
Independent Claim
217 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of gate oxide on the doped epitaxial silicon layer; forming a disposable gate on the gate oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the gate oxide; removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the gate oxide layer to expose the first epitaxial silicon substrate; forming an oxide with the first epitaxial silicon substrate layer, the oxide extending downwardly into the first epitaxial silicon substrate layer; removing the oxide to define a groove in the first epitaxial silicon substrate layer, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; forming a gate oxide in the recess on the exposed first epitaxial silicon substrate layer; and depositing a permanent gate material in the recess extending into the opposing laterally extended notches.
Claim 5
Independent Claim
185 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of pad oxide on the doped epitaxial silicon layer; forming a disposable gate on the pad oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the pad oxide; removing the pad oxide from the first epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the pad oxide layer to expose the first epitaxial silicon substrate and to expose portions of the second layer of epitaxial silicon; forming a gate oxide on the first epitaxial silicon substrate and exposed portions of the second layer of epitaxial silicon; and depositing a permanent gate material in the recess and in the second layer of epitaxial silicon.
Claim 6
Independent Claim
185 words
A method of forming a MOS transistor structure comprising the acts of: supplying a silicon substrate; positioning a first layer of doped epitaxial silicon on the silicon substrate; positioning a layer of pad oxide on the doped epitaxial silicon layer; forming a disposable gate on the pad oxide, the disposable gate having sidewalls; forming sidewall spacers on the disposable gate extending outwardly over the pad oxide; removing the pad oxide from the first epitaxial silicon layer except underneath the disposable gate; forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon; forming an interlayer dielectric over the second layer of epitaxial silicon and the gate; removing the dielectric from above the gate; removing the disposable gate to form a recess; removing the pad oxide layer to expose the first epitaxial silicon substrate and to expose portions of the second layer of epitaxial silicon; forming a gate oxide on the first epitaxial silicon substrate and exposed portions of the second layer of epitaxial silicon; and depositing a permanent gate material in the recess and in the second layer of epitaxial silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-03 | 2004-04-03 | 2004-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-03 | 2008-04-03 | 2008-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-03 | 2012-04-03 | 2012-10-03 | $7700.00 | Window Closed / Lapsed |