US5866459A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a contact structure for an MOS transistor entirely on isolation oxide
Assignee: National Semiconductor Corp
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Filing: 1997-02-20
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Granted: 1999-02-02
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Expires: 2017-02-20
Abstract
Abstract A MOS transistor structure is provided in which the source/drain contacts are to raised polysilicon and are located entirely over field isolation. Contact integrity is maintained because the contact is located on field oxide, rather than in direct contact with the substrate junction diffusion area. Conventional contact metal spiking into the junction area is also eliminated. Contact overetch during formation of the contact opening can be increased to insure a clean contact surface because the contact is made to the raised poly regions. Furthermore, the contact barrier is no longer essential for maintaining contact reliability, because the contact is located away from the active junction.
Inventors
- 👤 Abdalla Aly Naem
- 👤 Mohsen Shenasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/20; H10D64/23; H10D64/251; H10D64/258
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
323 words
A method of fabricating a MOSFET device structure in a silicon substrate, wherein the MOSFET device structure includes planarized trench isolation field oxide regions formed in the substrate, a layer of gate oxide formed on the substrate to electrically insulate a polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and gate oxide, LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate, the method comprising the steps of: depositing a layer of polysilicon on the above-defined structure; performing a chemical mechanical polishing step to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions; implanting N-type dopant into the polysilicon gate and into the raised source/drain polysilicon regions; performing a first rapid thermal processing (RTP) step to activate the N-type dopant implant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions; depositing a layer of cobalt on the polysilicon gate and on the raised source/drain polysilicon regions; implanting heavy ions into the cobalt layer to mix the cobalt and silicon at the interface of the cobalt layer and the underlying polysilicon; forming a TiN film on the cobalt layer; performing a second RTP step to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; removing unreacted cobalt; performing a third RTP step to form a stable salicide phase; forming a layer of dielectric material on the structure resulting from the above-recited steps; forming contact openings in the dielectric layer entirely over the trench field oxide isolation regions to expose the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; forming a conductive contact layer in the contact openings, and in electrical contact with the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.
Claim 2
Independent Claim
323 words
A method of fabricating a MOSFET device structure in a silicon substrate, wherein the MOSFET device structure includes planarized trench isolation field oxide regions formed in the substrate, a layer of gate oxide formed on the substrate to electrically insulate a polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and gate oxide, LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate, the method comprising the steps of: depositing a layer of polysilicon on the above-defined structure; performing a chemical mechanical polishing step to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions; implanting N-type dopant into the polysilicon gate and into the raised source/drain polysilicon regions; performing a first rapid thermal processing (RTP) step to activate the N-type dopant implant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions; depositing a layer of cobalt on the polysilicon gate and on the raised source/drain polysilicon regions; implanting heavy ions into the cobalt layer to mix the cobalt and silicon at the interface of the cobalt layer and the underlying polysilicon; forming a TiN film on the cobalt layer; performing a second RTP step to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; removing unreacted cobalt; performing a third RTP step to form a stable salicide phase; forming a layer of dielectric material on the structure resulting from the above-recited steps; forming contact openings in the dielectric layer entirely over the trench field oxide isolation regions to expose the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate; forming a conductive contact layer in the contact openings, and in electrical contact with the cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.
Claim 3
Dependent Claim
25 words
A method as in claim 1 and wherein the N-type dopant implanted into the polysilicon gate and into the raised source/drain polysilicon regions is arsenic.
Claim 4
Dependent Claim
18 words
A method as in claim 1 and wherein the heavy ions implanted into the cobalt layer comprise arsenic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |