EP0480446A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of fabricating a high-performance insulated-gate-field-effect transistor and transistor fabricated by it
Assignee: Texas Instruments Inc
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Filing: 1991-10-11
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Granted: —
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Expires: 2011-10-11
Abstract
Abstract An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.
Inventors
- 👤 Mehrdad M. Moslehi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 06:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/027; H10D30/0275; H10D30/60; H10D64/00; H10D64/01; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10P; H10P14/00; H10P14/40; H10P14/412; H10D64/017
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
68 words
A method of forming a transistor, comprising the steps of: forming an insulating layer adjacent a semiconductor region; forming a first gate conductor region adjacent the insulating layer and opposite the semiconductor region; and forming implanted source/drain regions within the semiconductor region by simultaneously implanting dopants into the gate conductor region and the semiconductor region; and forming a second gate conductor region adjacent the first gate conductor region.
Claim 2
Dependent Claim
19 words
The method of Claim 1 and further comprising forming elevated source/drain regions adjacent and overlying the implanted source/drain regions.
Claim 3
Dependent Claim
38 words
The method of Claim 2 wherein the elevated source/drain regions comprise a first pair of elevated doped source/drain regions, and further comprising forming a second pair of elevated source/drain regions overlying the first pair of elevated source/drain regions.
Claim 4
Independent Claim
30 words
A method as claimed in any preceding claim and wherein the gate conductor region includes sidewalls, and further comprising forming sidewall spacers adjacent the sidewalls of the gate conductor region.
Claim 5
Independent Claim
40 words
A method as claimed in any preceding claim and further comprising: covering selected regions of the transistor with a mask such that an area where an interconnect is to be formed is exposed; and implanting ions into the exposed area.
Claim 6
Dependent Claim
21 words
The method of Claim 5 and further comprising: removing the mask: and forming a semiconductor interconnect region in the exposed area.
Claim 7
Dependent Claim
20 words
The method of Claim 5 or Claim 6 and further comprising forming a reacted refractory metal contact inthe exposed area.
Claim 8
Dependent Claim
37 words
The method of Claim 7 wherein said step of forming a reacted refractory metal contact comprises: sputtering refractory metal over the exposed areas; and annealing the refractory metal such that it reacts with the semiconductor interconnect region.
Claim 9
Independent Claim
46 words
A method as claimed in any preceding claim and further comprising: forming an etch stop layer adjacent the first gate conductor region and opposite the first insulating layer; and forming a disposable gate region adjacent the etch stop layer and opposite the first gate conductor region.
Claim 10
Dependent Claim
57 words
The method of Claim 8 and further comprising : forming a nitride pad layer adjacent the disposable gate region and opposite the etch stop layer, wherein the first gate conductor region, the etch stop layer and the disposable gate region include sidewalls; forming sidewalls spacers adjacent the sidewalls; and forming oxide sidewall spacers adjacent the sidewall spacers.
Claim 11
Dependent Claim
90 words
A method of forming a transistor, as claimed in claim 1 and wherein said insulating layer is formed to have sidewalls; said first gate conductor region is formed to have sidewalls and said second gate conductor region is formed as a disposable region having sidewalls and futher comprising the steps of forming an etch stop layer having sidewalls adjacent the first gate conductor and opposite the first insulating layer; and forming sidewall spacers adjacent the sidewalls of the insulating layer, gate conductor region, etch stop layer and disposable gate region;
Claim 12
Dependent Claim
26 words
The method of Claim 11 and further comprising: removing the etch stop layer; and forming a third gate coductor region adjacent the first gate conductor region.
Claim 13
Dependent Claim
36 words
The method of Claim 11 or claim 12 and further comprising: forming a nitride pad adjacent the disposable gate region and opposite the etch stop layer, and wherein the sidewall spacers comprise oxide nitride sidewall spacers.
Claim 14
Dependent Claim
32 words
The method of Claim 11, 12 or 13 and further comprising: forming semiconductor extension segments contacting the elevated source/drain regions; and forming a reacted refractory metal layer contacting the elevated source/drain regions.
Claim 15
Independent Claim
25 words
A method as claimed in any of claims 11 to 14 and further comprising forming a reacted refractory metal layer overlying said gate conductor region.
Claim 16
Independent Claim
75 words
A method as claimed in any preceding claim and wherein the transistor is included within an integrated circuit, and further comprising: covering a selected region of the integrated circuit with a mask such that an area where an interconnect is to be formed is exposed; and implanting ions into the exposed area; removing the mask; forming a semiconductor interconnect region in the exposed area; and forming a reacted refractory metal contact in the exposed area.
Claim 17
Dependent Claim
46 words
A transistor, comprising: an insulating layer adjacent a semiconductor region; a first gate conductor region adjacent said insulating layer and opposite said semiconductor region; and a pair of implanted source/drain regions within said semiconductor region; a second gate conductor region adjacent said first gate conductor region.
Claim 18
Dependent Claim
33 words
The transistor of Claim 17 wherein said pair of implanted source/drain regions comprise heavily doped source/drain regions, and further comprising a pair of lightly-doped drain source/drain regions contacting said heavily doped source/drain regions.
Claim 19
Dependent Claim
24 words
The transistor of Claim 17 or Claim 18 and further comprising a pair of elevated source/drain regions adjacent and overlying said implanted source/drain regions.
Claim 20
Dependent Claim
37 words
The transistor of Claim 19 wherein said elevated source/drain regions comprise a first pair of elevated doped source/drain regions, and further comprising a second pair of elevated source/drain regions overlying said first pair of elevated source/drain regions.
Claim 21
Dependent Claim
31 words
A transistor as claimed in any of claims 17 to 20 and wherein said gate conductor region includes sidewalls, and further comprising sidewall spacers adjacent said sidewalls of said gate conductor.
Claim 22
Dependent Claim
43 words
A transistor as claimed in any of claims 17 to 21 and further comprising: an etch stop layer adjacent said first conductor and opposite said first insulating layer; and a disposable gate region adjacent said etch layer and opposite said first gate conductor.
Claim 23
Dependent Claim
57 words
The transistor of Claim 22 and further comprising: a nitride pad adjacent said disposable gate region and opposite said etch stop layer, wherein said first gate conductor, said etch stop layer and said disposable gate region include sidewalls; a pair of sidewall spacers adjacent said sidewalls; and a pair of oxide sidewall spacers adjacent said sidewall spacers.
Claim 24
Dependent Claim
15 words
An intergrated circuit including a transistor as claimed in any of claims 17 to 23.
References Cited (Backward Citations)
No citation records indexed.
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