Patent US6100171A successfully refreshed from Google Patents.
US6100171A
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Reduction of boron penetration by laser anneal removal of fluorine
Assignee: Advanced Micro Devices Inc
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Filing: 1998-03-03
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Granted: 2000-08-08
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Expires: 2018-03-03
Abstract
Abstract In one embodiment, the present invention relates to a method of removing fluorine from a gate conductor involving the steps of providing a semiconductor device containing a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor containing fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt at least a portion of the gate conductor thereby inducing the removal of fluorine from the gate conductor. In another embodiment, the present invention relates to a method of making a transistor involving the steps of forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF 2 + to form in the substrate a source region and a drain region adjacent the gate insulator layer and a channel region between the source and drain regions and under the gate insulator layer; laser annealing the doped gate conductor, the doped source region and the doped drain region at an energy level sufficient to melt at least a portion of the doped gate conductor, thereby removing fluorine from the melted portion of the gate conductor; and subsequently performing an RTA to activate the doped source region and the doped drain region
Inventors
- 👤 Emi Ishida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10P; H10P34/00; H10P34/40; H10P34/42
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
78 words
A method of removing fluorine from a gate conductor, comprising: providing a semiconductor device comprising a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor comprising fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt only a portion of the gate conductor thereby inducing removal of fluorine from the gate conductor.
Claim 2
Independent Claim
78 words
A method of removing fluorine from a gate conductor, comprising: providing a semiconductor device comprising a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor comprising fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt only a portion of the gate conductor thereby inducing removal of fluorine from the gate conductor.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein the gate conductor comprising fluorine is BF 2 + doped polysilicon.
Claim 4
Dependent Claim
18 words
The method of claim 1, wherein laser annealing comprises irradiating with an excimer laser in a pulsed mode.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein laser annealing comprises irradiating with an excimer laser with an energy fluence of about 0.5 to about 0.9 J/cm 2 .
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein laser annealing comprises irradiating with an excimer laser with an energy fluence of about 0.6 to about 0.8 J/cm 2 .
Claim 7
Dependent Claim
28 words
The method of claim 1, wherein the portion of the gate conductor melted is equivalent to a depth of about one-half of the thickness of the gate conductor.
Claim 8
Dependent Claim
34 words
The method of claim 1, wherein laser annealing is performed at an energy level sufficient to melt at least a portion of the gate conductor but insufficient to melt the source and drain regions.
Claim 9
Dependent Claim
23 words
The method of claim 1, wherein the gate conductor comprises less fluorine after laser annealing than the gate conductor comprises before laser annealing.
Claim 10
Independent Claim
131 words
A method of making a transistor, comprising: forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF 2 + to form in the substrate a source region and a drain region adjacent the gate insulator layer and a channel region between the source and drain regions and under the gate insulator layer; laser annealing the doped gate conductor, the doped source region and the doped drain region at an energy level sufficient to melt only a portion of the doped gate conductor, thereby removing fluorine from the melted portion of the gate conductor; and subsequently performing an RTA to activate the doped source region and the doped drain region.
Claim 11
Independent Claim
131 words
A method of making a transistor, comprising: forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF 2 + to form in the substrate a source region and a drain region adjacent the gate insulator layer and a channel region between the source and drain regions and under the gate insulator layer; laser annealing the doped gate conductor, the doped source region and the doped drain region at an energy level sufficient to melt only a portion of the doped gate conductor, thereby removing fluorine from the melted portion of the gate conductor; and subsequently performing an RTA to activate the doped source region and the doped drain region.
Claim 12
Dependent Claim
27 words
The method of claim 9, wherein doping the gate conductor, the source region and the drain region comprises subjecting the gate conductor and substrate to ion implantation.
Claim 13
Dependent Claim
43 words
The method of claim 10, wherein ion implantation comprises the step of implanting BF 2 + at a concentration from about 5×10 13 ions/cm 2 to about 5×10 15 ions/cm 2 and an implantation energy from about 1 keV to about 50 keV.
Claim 14
Dependent Claim
27 words
The method of claim 9, wherein laser annealing comprises irradiating with an excimer laser with an energy fluence of about 0.5 to about 0.9 J/cm 2 .
Claim 15
Dependent Claim
18 words
The method of claim 9, wherein laser annealing is performed with an excimer laser in a pulsed mode.
Claim 16
Dependent Claim
15 words
The method of claim 9, wherein laser annealing is performed with an XeCl excimer laser.
Claim 17
Dependent Claim
30 words
The method of claim 9, wherein the portion of the doped gate conductor melted is equivalent to a depth of about one-half of the thickness of the doped gate conductor.
Claim 18
Independent Claim
122 words
A method of reducing dopant diffusion from a doped gate conductor to an underlying gate insulator or channel region, comprising: providing a semiconductor device comprising a substrate, a gate insulator layer overlying a portion of the substrate, a doped gate conductor overlying the gate insulator layer, a source and a drain region adjacent the gate insulator layer, and a channel region below the gate insulator layer and between the source and drain region; and laser annealing the semiconductor device using an excimer laser with an energy fluence of about 0.5 to about 0.9 J/cm 2 to melt only a portion of the doped gate conductor thereby reducing dopant diffusion from the doped gate conductor to the underlying gate insulator or channel region.
Claim 19
Independent Claim
122 words
A method of reducing dopant diffusion from a doped gate conductor to an underlying gate insulator or channel region, comprising: providing a semiconductor device comprising a substrate, a gate insulator layer overlying a portion of the substrate, a doped gate conductor overlying the gate insulator layer, a source and a drain region adjacent the gate insulator layer, and a channel region below the gate insulator layer and between the source and drain region; and laser annealing the semiconductor device using an excimer laser with an energy fluence of about 0.5 to about 0.9 J/cm 2 to melt only a portion of the doped gate conductor thereby reducing dopant diffusion from the doped gate conductor to the underlying gate insulator or channel region.
Claim 20
Dependent Claim
27 words
The method of claim 16, wherein laser annealing comprises irradiating with an excimer laser with an energy fluence of about 0.6 to about 0.8 J/cm 2 .
Claim 21
Dependent Claim
17 words
The method of claim 16, wherein the doped gate conductor provided comprises BF 2 + doped polysilicon.
Claim 22
Dependent Claim
35 words
The method of claim 16, wherein laser annealing is performed at an energy level sufficient to melt at least a portion of the doped gate conductor but insufficient to melt the source and drain regions.
Claim 23
Dependent Claim
16 words
The method of claim 16, wherein the semiconductor device has a lightly doped drain type structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-08 | 2004-02-07 | 2004-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-08 | 2008-02-07 | 2008-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-08 | 2012-02-07 | 2012-08-08 | $7700.00 | Window Closed / Lapsed |