US4764478A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing MOS transistor by dual species implantation and rapid annealing
Assignee: Toshiba Corp
•
Filing: 1986-11-20
•
Granted: 1988-08-16
•
Expires: 2006-11-20
Abstract
Abstract A semiconductor apparatus manufacturing method which is characterized in that the process of distributing an impurity in the gate electrode of the semiconductor apparatus is improved by the steps of depositing a gate oxide layer on a silicon substrate, mounting a polycrystalline silicon layer on said gate oxide layer, introducing boron as a first impurity in the surface of said polycrystalline silicon layer by the vapor phase diffusion process, solid phase diffusion process or ion implantation, ion-implanting arsenic or silicon, boron difluoride as a second impurity having a greater mass than the first impurity, and ensuring the uniform redistribution of the first impurity in the polycrystalline silicon layer by annealing or a Lamp Anneal process which is carried out at a low temperature and for a short time.
Inventors
- 👤 Yoichi Hiruta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:58
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/30; H10P32/302; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/60; H10D64/66; H10D64/661
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
80 words
A method for manufacturing a semiconductor device comprising the steps of: depositing an insulation layer on a surface of a semiconductor substrate; mounting a polycrystalline silicon layer on said insulation layer; ion-implanting boron at a region in the proximity of the surface of said polycrystalline silicon layer; and after said ion-implanting of boron, ion-implanting arsenic at said region at a dose smaller than that of said boron to effect a uniform redistribution of said boron in said polycrystalline silicon layer.
Claim 2
Independent Claim
80 words
A method for manufacturing a semiconductor device comprising the steps of: depositing an insulation layer on a surface of a semiconductor substrate; mounting a polycrystalline silicon layer on said insulation layer; ion-implanting boron at a region in the proximity of the surface of said polycrystalline silicon layer; and after said ion-implanting of boron, ion-implanting arsenic at said region at a dose smaller than that of said boron to effect a uniform redistribution of said boron in said polycrystalline silicon layer.
Claim 3
Dependent Claim
29 words
The method according to claim 1, wherein said boron is ion-implanted at an acceleration energy of approximately 35 keV, at a dose of approximately 1×10 16 cm -2 .
Claim 4
Dependent Claim
29 words
The method according to claim 1, wherein said arsenic is ion-implanted at an acceleration energy of approximately 40 keV, at a dose of approximately 2×10 15 cm -2 .
Claim 5
Dependent Claim
26 words
The method according to claim 1, wherein after the uniform redistribution of said boron in said polycrystalline silicon layer, annealing is performed to activate said boron.
Claim 6
Dependent Claim
27 words
The method according to claim 1, wherein after the redistribution of said boron in said polycrystalline silicon layer, Lamp Anneal process is performed to activate said boron.
Claim 7
Dependent Claim
26 words
The method according to claim 1, wherein said ion implantation of arsenic is effected after a gate electrode is formed by patterning said polycrystalline silicon layer.
Claim 8
Independent Claim
95 words
A method for manufacturing a semiconductor device comprising the steps of: depositing an insulation layer on a surface of a semiconductor substrate; mounting a polycrystalline silicon layer on said insulation layer; introducing a first impurity of a predetermined conductivity type at a region in the proximity of the surface of said polycrystalline silicon layer by vapor phase diffusion; and after said introducing of said first impurity, ion-implanting a second impurity at said region having a greater mass than said first impurity to effect a uniform redistribution of said first impurity in said polycrystalline silicon layer.
Claim 9
Independent Claim
95 words
A method for manufacturing a semiconductor device comprising the steps of: depositing an insulation layer on a surface of a semiconductor substrate; mounting a polycrystalline silicon layer on said insulation layer; introducing a first impurity of a predetermined conductivity type at a region in the proximity of the surface of said polycrystalline silicon layer by vapor phase diffusion; and after said introducing of said first impurity, ion-implanting a second impurity at said region having a greater mass than said first impurity to effect a uniform redistribution of said first impurity in said polycrystalline silicon layer.
Claim 10
Dependent Claim
19 words
The method according to claim 7 wherein said vapor phase diffusion is performed in an atmosphere of boron trichloride.
Claim 11
Dependent Claim
22 words
The method according to claim 7, wherein said first impurity of a predetermined conductivity type is introduced by solid phase diffusion process.
Claim 12
Dependent Claim
21 words
The method according to claim 7, wherein activation of said first impurity in said polycrystalline silicon layer is effected by annealing.
Claim 13
Dependent Claim
23 words
The method according to claim 7, wherein activation of said first impurity of said polycrystalline silicon layer is effected by Lamp Anneal process.
Claim 14
Dependent Claim
36 words
The method according to claim 7, wherein said ion implantation of said second impurity having a greater mass than said first impurity is effected after a gate electrode is formed by patterning said polycrystalline silicon layer.
Claim 15
Dependent Claim
14 words
The method according to claim 7, wherein said first impurity is formed of boron.
Claim 16
Dependent Claim
14 words
The method according to claim 7, wherein said second impurity is prepared from arsenic.
Claim 17
Dependent Claim
13 words
The method according to claim 7, wherein said second impurity consists of silicon.
Claim 18
Dependent Claim
15 words
The method according to claim 7, wherein said second impurity is formed from boron difluoride.
Claim 19
Dependent Claim
13 words
The method according to claim 7, wherein said second impurity consists of argon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-16 | 1992-02-15 | 1992-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-16 | 1996-02-15 | 1996-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-16 | 2000-02-15 | 2000-08-16 | $7700.00 | Window Closed / Lapsed |