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US6097781A
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Shared counter
Assignee: Micron Technology Inc
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Filing: 1998-02-02
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Granted: 2000-08-01
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Expires: 2018-02-02
Abstract
Abstract A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.
Inventors
- 👤 Jeffrey P. Wright
- 👤 Hua Zheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:31
CPC Classifications
H; H03; H03K; H03K21/00
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
120 words
A memory device, comprising: at least one memory array arranged in rows and columns; a shared counter, wherein the shared counter includes: a counter circuit for performing multiple counting functions on counter input data to provide counter output data, and an output circuit receiving the counter output data and providing the counter output data to one of K output lines, wherein K is at least two; a column address decoder receiving the counter output data on a first one of the K output lines from the shared counter to identify a column of the at least one memory array; and first circuitry receiving the counter output data on a second one of the K output lines from the shared counter.
Claim 2
Dependent Claim
120 words
A memory device, comprising: at least one memory array arranged in rows and columns; a shared counter, wherein the shared counter includes: a counter circuit for performing multiple counting functions on counter input data to provide counter output data, and an output circuit receiving the counter output data and providing the counter output data to one of K output lines, wherein K is at least two; a column address decoder receiving the counter output data on a first one of the K output lines from the shared counter to identify a column of the at least one memory array; and first circuitry receiving the counter output data on a second one of the K output lines from the shared counter.
Claim 3
Dependent Claim
15 words
The memory device of claim 1, wherein the first circuitry includes a row address decoder.
Claim 4
Dependent Claim
89 words
The memory device of claim 1, wherein the shared counter further includes: a first buffer adapted to receive the counter output data from the counter circuit and store first buffer data corresponding to counter output data provided as a result of a first counting function; and a multiplexer circuit coupled to receive a plurality of counter data sets including initialization data and the first buffer data, the multiplexer circuit providing a selected one of the plurality of counter data sets as the counter input data to the counter circuit.
Claim 5
Dependent Claim
44 words
The memory device of claim 3, wherein the memory device further includes a second buffer adapted to receive counter output data from the counter circuit and store second buffer data corresponding to counter output data provided as a result of a second counting function.
Claim 6
Dependent Claim
30 words
The memory device of claim 1, wherein the shared counter further includes an input selection circuit selecting one of M input data sets to be provided as counter input data.
Claim 7
Dependent Claim
16 words
The memory device of claim 1, wherein the device is a dynamic random access memory (DRAM).
Claim 8
Dependent Claim
16 words
The memory device of claim 1, wherein the device is a static random access memory (SRAM).
Claim 9
Dependent Claim
16 words
The memory device of claim 1, wherein the device is a video random access memory (VRAM).
Claim 10
Dependent Claim
17 words
The memory device of claim 1, wherein the device is a synchronous graphic random access memory (SGRAM).
Claim 11
Dependent Claim
25 words
The memory device of claim 1, wherein the shared counter performs a self-refresh timing function, an auto refresh counting function, and a burst counting function.
Claim 12
Dependent Claim
70 words
The memory device of claim 1, wherein the memory device further includes a clock circuit providing a first clock signal having a first clock frequency for use by the shared counter during a first of the multiple counting functions, and providing a second clock signal having a second clock frequency different than the first clock frequency for use by the shared counter during a second of the multiple counting functions.
Claim 13
Independent Claim
110 words
A method of performing multiple counting functions in a shared counter, comprising: selecting a first initialization data; counting the first initialization data up or down using the shared counter to provide a first counter output data; storing the first counter output data set after performing the counting step corresponding to the first counting function; selecting a second initialization data; counting the second initialization data up or down using the shared counter to provide a second counter output data set; retrieving the first counter output data set; and counting the first counter output data set up or down using the shared counter to provide an updated first counter output data set.
Claim 14
Independent Claim
110 words
A method of performing multiple counting functions in a shared counter, comprising: selecting a first initialization data; counting the first initialization data up or down using the shared counter to provide a first counter output data; storing the first counter output data set after performing the counting step corresponding to the first counting function; selecting a second initialization data; counting the second initialization data up or down using the shared counter to provide a second counter output data set; retrieving the first counter output data set; and counting the first counter output data set up or down using the shared counter to provide an updated first counter output data set.
Claim 15
Dependent Claim
25 words
The method of claim 12, wherein storing the first counter output data set includes storing the first counter output data set in a first buffer.
Claim 16
Dependent Claim
27 words
The method of claim 12, wherein the method further includes storing the second counter output data set in a second buffer corresponding to the second counting function.
Claim 17
Dependent Claim
21 words
The method of claim 14, wherein the method further includes retrieving the second counter output data set, from the second buffer.
Claim 18
Dependent Claim
21 words
The method of claim 14, wherein the method further includes retrieving the first counter output data set, from the first buffer.
Claim 19
Dependent Claim
29 words
The method of claim 14, wherein the method further includes using the second counter output data set to provide a memory address for use during a memory refresh operation.
Claim 20
Dependent Claim
29 words
The method of claim 14, wherein the method further includes using the first counter output data set to provide a memory address for use during a memory refresh operation.
Claim 21
Dependent Claim
60 words
The method of claim 14, wherein the method further includes: providing the first counter output data set to a first destination circuit at a first time; providing the second counter output data set to a second destination circuit at a second time; and providing the updated first counter output data set to the first destination circuit at a third time.
Claim 22
Independent Claim
84 words
A method of performing multiple counting functions in a memory device, comprising: receiving address input data in a shared counter, wherein the shared counter includes a counter circuit and a number of buffer circuits; and performing multiple counting functions in the counter circuit in order to provide multiple outputs, wherein one output includes column address output data for accessing memory addresses in a memory array, and wherein another output includes buffer data to provide a memory address for use during a memory refresh operation.
Claim 23
Independent Claim
84 words
A method of performing multiple counting functions in a memory device, comprising: receiving address input data in a shared counter, wherein the shared counter includes a counter circuit and a number of buffer circuits; and performing multiple counting functions in the counter circuit in order to provide multiple outputs, wherein one output includes column address output data for accessing memory addresses in a memory array, and wherein another output includes buffer data to provide a memory address for use during a memory refresh operation.
Claim 24
Dependent Claim
47 words
The method of claim 20, wherein the method further includes routing the output data for use in accessing rows or columns of a first memory array at a first time and for use in accessing rows or columns of a second memory array at a second time.
Claim 25
Dependent Claim
42 words
The method of claim 20, wherein the method further includes routing first buffer data to a first buffer circuit in response to a first control signal and second buffer data to a second buffer circuit in response to a second control signal.
Claim 26
Dependent Claim
40 words
The method of claim 22, wherein receiving address input data includes receiving address input data from the first buffer circuit in response to a first control signal and from the second buffer circuit in response to a second control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |