US6096643A
Expired / Lapsed
US
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Method of fabricating a semiconductor device having polysilicon line with extended silicide layer
Assignee: Advanced Micro Devices Inc
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Filing: 1998-10-01
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Granted: 2000-08-01
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Expires: 2018-10-01
Abstract
Abstract A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.
Inventors
- 👤 Homi E. Nariman
- 👤 H. Jim Fulford
- 👤 Charles E. May
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/064; H10W20/066; H10W20/0698
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
76 words
A process of forming a semiconductor device, comprising: forming a polysilicon line on a substrate; forming a dielectric layer over the substrate and adjacent the polysilicon line; forming a patterned metal layer over the polysilicon line and the dielectric layer said metal layer directly contacting the polysilicon line; forming a polysilicon layer over the patterned metal layer; and forming a silicide layer over the polysilicon line by reacting the patterned metal layer and the polysilicon layer.
Claim 2
Dependent Claim
76 words
A process of forming a semiconductor device, comprising: forming a polysilicon line on a substrate; forming a dielectric layer over the substrate and adjacent the polysilicon line; forming a patterned metal layer over the polysilicon line and the dielectric layer said metal layer directly contacting the polysilicon line; forming a polysilicon layer over the patterned metal layer; and forming a silicide layer over the polysilicon line by reacting the patterned metal layer and the polysilicon layer.
Claim 3
Dependent Claim
36 words
The process of claim 1, wherein forming the dielectric layer includes depositing a dielectric material over the substrate and the polysilicon line and polishing the dielectric layer to expose an upper surface of the polysilicon line.
Claim 4
Dependent Claim
20 words
The process of claim 1, further including forming source/drain regions adjacent the polysilicon line prior to forming the dielectric layer.
Claim 5
Dependent Claim
20 words
The process of claim 1, wherein forming the patterned metal layer includes depositing a metal and selectively etching the metal.
Claim 6
Dependent Claim
48 words
The process of claim 1, wherein forming the patterned metal layer includes forming edges of the patterned metal layer which extend beyond edges of the polysilicon line and wherein forming the silicide layer includes forming the silicide layer with edges extending beyond the edges of the polysilicon line.
Claim 7
Dependent Claim
28 words
The process of claim 5, wherein the patterned metal layer edges extend beyond the edges of the polysilicon line by about half the width of the polysilicon line.
Claim 8
Dependent Claim
14 words
The process of claim 1, wherein the patterned metal layer is formed from cobalt.
Claim 9
Dependent Claim
101 words
The process of claim 1, wherein: forming the polysilicon line includes forming a second polysilicon line; forming the dielectric layer includes forming the dielectric layer adjacent the second polysilicon line; forming the patterned metal layer includes forming the patterned metal layer over the second polysilicon line; and forming the silicide layer includes forming the silicide layer over the second polysilicon line; wherein a portion of the patterned metal layer over the polysilicon line is connected to a portion of the patterned metal layer over the second polysilicon line such that the silicide layer forms a local interconnect between the polysilicon lines.
Claim 10
Dependent Claim
109 words
A process of forming a semiconductor device, comprising: forming a gate electrode on a substrate; depositing a dielectric layer over the substrate and removing the dielectric layer to expose the gate electrode; depositing a metal layer over the gate electrode and the dielectric layer said metal layer directly contacting the gate electrode; selectively etching the metal layer to leave a patterned metal layer having edges extending beyond edges of the gate electrode; depositing a polysilicon layer over the patterned metal layer; and reacting the patterned metal layer and the polysilicon layer to form a silicide layer over the gate electrode and extending beyond the edges of the gate electrode.
Claim 11
Dependent Claim
109 words
A process of forming a semiconductor device, comprising: forming a gate electrode on a substrate; depositing a dielectric layer over the substrate and removing the dielectric layer to expose the gate electrode; depositing a metal layer over the gate electrode and the dielectric layer said metal layer directly contacting the gate electrode; selectively etching the metal layer to leave a patterned metal layer having edges extending beyond edges of the gate electrode; depositing a polysilicon layer over the patterned metal layer; and reacting the patterned metal layer and the polysilicon layer to form a silicide layer over the gate electrode and extending beyond the edges of the gate electrode.
Claim 12
Dependent Claim
23 words
The process of claim 9, wherein forming the silicide layer includes reacting the patterned metal layer with a portion of the gate electrode.
Claim 13
Dependent Claim
104 words
A process of forming a semiconductor device, comprising: forming first and second polysilicon lines on a substrate; forming a dielectric layer over the substrate and adjacent the first and second polysilicon lines; forming a patterned metal layer having first and second metal lines respectively disposed over and directly contacting the first and second polysilicon lines and a portion connecting the first and second metal lines; forming a polysilicon layer over the patterned metal layer; and reacting the patterned metal layer and the polysilicon layer to form a silicide layer over the first and second polysilicon lines and interconnecting the first and second polysilicon lines.
Claim 14
Dependent Claim
104 words
A process of forming a semiconductor device, comprising: forming first and second polysilicon lines on a substrate; forming a dielectric layer over the substrate and adjacent the first and second polysilicon lines; forming a patterned metal layer having first and second metal lines respectively disposed over and directly contacting the first and second polysilicon lines and a portion connecting the first and second metal lines; forming a polysilicon layer over the patterned metal layer; and reacting the patterned metal layer and the polysilicon layer to form a silicide layer over the first and second polysilicon lines and interconnecting the first and second polysilicon lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |