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US6093632A
Expired / Lapsed
US
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Modified dual damascene process
Assignee: Industrial Technology Research Institute
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Filing: 1998-12-07
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Granted: 2000-07-25
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Expires: 2018-12-07
Abstract
Abstract A process for creating a metal filled, dual damascene opening, in a composite insulator layer, has been developed. The process features selective RIE procedures, used to create a wide diameter opening in an upper silicon oxide layer, and a narrow diameter opening in a lower silicon oxide layer. Small area, silicon nitride islands, or shapes, a component of the composite insulator layer, are used as a stop layer, during the selective RIE procedures. The use of small area, silicon nitride shapes, offers less composite insulator capacitance, than counterparts fabricated using larger area, silicon nitride stop layers.
Inventors
- 👤 Kang-Cheng Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/086
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
365 words
A method of fabricating a metal structure, on a semiconductor substrate, with the metal structure featuring a wide, metal shape, on underlying, narrow metal shape, comprising the steps of: providing a first metal interconnect structure, located in an opening in a first insulator layer; depositing a first silicon nitride layer, a second insulator layer, and a second silicon nitride layer, on the top surface of said first metal interconnect structure, and on the top surface of said first insulator layer; patterning of said second silicon nitride layer, to form silicon nitride islands, with narrow spaces between said silicon nitride islands, exposing a portion of the top surface of underlying, said second insulator layer; depositing a third insulator layer; forming a photoresist shape, on said third insulator layer, featuring a wide opening in said photoresist shape, exposing a portion of the top surface of said third insulator layer; performing a selective, first dry etching procedure, using said wide opening, in said photoresist shape as a mask, to create a wide diameter opening, in said third insulator layer, exposing a portion of said silicon nitride islands, and exposing a narrow space, located between said silicon nitride islands, then continuing said selective, first dry etching procedure, to create a narrow diameter opening in said second insulator layer, using portions of said silicon nitride islands, exposed in said wide diameter opening, as a mask, to create a narrow diameter opening in said second insulator layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening; performing a selective, second dry etching procedure, to remove portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure, and removing portions of said silicon nitride islands, exposed in said wide diameter opening; and forming said metal structure, comprised of said wide metal shape, located in said wide diameter opening, and comprised of said narrow metal, located in said narrow diameter opening, with said narrow metal shape, overlying and contacting, the portion of said first metal interconnect structure, exposed at the bottom of said narrow diameter opening.
Claim 2
Independent Claim
365 words
A method of fabricating a metal structure, on a semiconductor substrate, with the metal structure featuring a wide, metal shape, on underlying, narrow metal shape, comprising the steps of: providing a first metal interconnect structure, located in an opening in a first insulator layer; depositing a first silicon nitride layer, a second insulator layer, and a second silicon nitride layer, on the top surface of said first metal interconnect structure, and on the top surface of said first insulator layer; patterning of said second silicon nitride layer, to form silicon nitride islands, with narrow spaces between said silicon nitride islands, exposing a portion of the top surface of underlying, said second insulator layer; depositing a third insulator layer; forming a photoresist shape, on said third insulator layer, featuring a wide opening in said photoresist shape, exposing a portion of the top surface of said third insulator layer; performing a selective, first dry etching procedure, using said wide opening, in said photoresist shape as a mask, to create a wide diameter opening, in said third insulator layer, exposing a portion of said silicon nitride islands, and exposing a narrow space, located between said silicon nitride islands, then continuing said selective, first dry etching procedure, to create a narrow diameter opening in said second insulator layer, using portions of said silicon nitride islands, exposed in said wide diameter opening, as a mask, to create a narrow diameter opening in said second insulator layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening; performing a selective, second dry etching procedure, to remove portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure, and removing portions of said silicon nitride islands, exposed in said wide diameter opening; and forming said metal structure, comprised of said wide metal shape, located in said wide diameter opening, and comprised of said narrow metal, located in said narrow diameter opening, with said narrow metal shape, overlying and contacting, the portion of said first metal interconnect structure, exposed at the bottom of said narrow diameter opening.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said first silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 300 Angstroms.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein said second insulator layer is silicon oxide, obtained via LPCVD or PECVD procedures, at a thickness between about 4000 to 15000 Angstroms.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein said second silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 2000 Angstroms.
Claim 6
Dependent Claim
59 words
The method of claim 1, wherein said silicon nitride islands are formed via an anisotropic RIE procedure, performed to said second silicon nitride layer, using a fluorine based gas, such as CHF 3 , CH 2 F 2 , or CH 3 F, as an etchant, with a space between said silicon nitride islands, of at least 500 Angstroms.
Claim 7
Dependent Claim
28 words
The method of claim 1, wherein said third insulator layer is silicon oxide, obtained via LPCVD or PECVD procedures, at a thickness between about 3000 to 15000 Angstroms.
Claim 8
Dependent Claim
47 words
The method of claim 1, wherein said selective, first dry etching procedure, used to create said wide diameter opening, in said third insulator layer, and to create said narrow diameter opening, in said second insulator layer, is an anisotropic RIE procedure, using CHF 3 as an etchant.
Claim 9
Dependent Claim
25 words
The method of claim 1, wherein the diameter of said wide diameter opening, in said third insulator layer, is between about 1500 to 10000 Angstroms.
Claim 10
Dependent Claim
25 words
The method of claim 1, wherein the diameter of said narrow diameter opening, in said second insulator layer, is between about 1500 to 5000 Angstroms.
Claim 11
Dependent Claim
72 words
The method of claim 1, wherein said selective, second dry etching procedure, used to remove the portion of said first silicon nitride layer, exposed in said narrow diameter opening, and to remove the portions of said silicon nitride islands, exposed in said wide diameter opening, is an anisotropic RIE procedure, using a fluorine based gas, such as CHF 3 , CH 2 F 2 , or CH 3 F, as an etchant.
Claim 12
Dependent Claim
25 words
The method of claim 1, wherein said metal structure, formed in said wide diameter opening, and in said narrow diameter opening, is comprised of copper.
Claim 13
Independent Claim
375 words
A method of forming a metal structure, on a semiconductor substrate, comprised of a wide metal shape, on an underlying narrow metal shape, using a dual damascene process, and using silicon nitride islands as an etch stop, during the patterning of a dual damascene opening, in a composite insulator layer, comprising the steps of: providing a first silicon oxide layer, with an opening in said first silicon oxide layer; forming a first metal interconnect structure, in said opening in said first silicon oxide layer; depositing a first silicon nitride layer; depositing a second silicon oxide layer; depositing a second silicon nitride layer; patterning of said second silicon nitride layer, to create said silicon nitride islands, on said second silicon oxide layer, and creating a narrow space between said silicon nitride islands, exposing a portion of the top surface of said second silicon oxide layer; depositing a third silicon oxide layer; forming a photoresist shape, with a wide diameter opening in said photoresist shape, exposing a portion of the top surface of said third silicon oxide layer; performing a selective, first RIE procedure, using said wide diameter opening, in said photoresist shape, as a mask, to create a wide diameter opening, in said third silicon oxide layer, than using portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, as a mask, to create a narrow diameter opening, in said second silicon oxide layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening; performing a selective, second RIE procedure, removing said portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, and removing said portion of said first silicon nitride layer, exposed at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure; depositing a metal layer; and removing portions of metal layer from the top surface of said third silicon oxide layer, forming said metal structure in said dual damascene opening, with said metal structure comprised of a wide metal shape, located in said wide diameter opening, and comprised of a narrow metal shape, located in said narrow diameter opening.
Claim 14
Independent Claim
375 words
A method of forming a metal structure, on a semiconductor substrate, comprised of a wide metal shape, on an underlying narrow metal shape, using a dual damascene process, and using silicon nitride islands as an etch stop, during the patterning of a dual damascene opening, in a composite insulator layer, comprising the steps of: providing a first silicon oxide layer, with an opening in said first silicon oxide layer; forming a first metal interconnect structure, in said opening in said first silicon oxide layer; depositing a first silicon nitride layer; depositing a second silicon oxide layer; depositing a second silicon nitride layer; patterning of said second silicon nitride layer, to create said silicon nitride islands, on said second silicon oxide layer, and creating a narrow space between said silicon nitride islands, exposing a portion of the top surface of said second silicon oxide layer; depositing a third silicon oxide layer; forming a photoresist shape, with a wide diameter opening in said photoresist shape, exposing a portion of the top surface of said third silicon oxide layer; performing a selective, first RIE procedure, using said wide diameter opening, in said photoresist shape, as a mask, to create a wide diameter opening, in said third silicon oxide layer, than using portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, as a mask, to create a narrow diameter opening, in said second silicon oxide layer, exposing a portion of said first silicon nitride layer, located at the bottom of said narrow diameter opening; performing a selective, second RIE procedure, removing said portions of said silicon nitride islands, exposed in said wide diameter opening, in said third silicon oxide layer, and removing said portion of said first silicon nitride layer, exposed at the bottom of said narrow diameter opening, exposing a portion of the top surface of said first metal interconnect structure; depositing a metal layer; and removing portions of metal layer from the top surface of said third silicon oxide layer, forming said metal structure in said dual damascene opening, with said metal structure comprised of a wide metal shape, located in said wide diameter opening, and comprised of a narrow metal shape, located in said narrow diameter opening.
Claim 15
Dependent Claim
35 words
The method of claim 12, wherein said first metal interconnect structure is comprised of a titanium titanium--nitride, adhesive--barrier layer, on the sides of said opening in said first silicon oxide layer, and filled with copper.
Claim 16
Dependent Claim
27 words
The method of claim 12, wherein said first silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 300 Angstroms.
Claim 17
Dependent Claim
27 words
The method of claim 12, wherein said second silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 4000 to 15000 Angstroms.
Claim 18
Dependent Claim
27 words
The method of claim 12, wherein said second silicon nitride layer is obtained via LPCVD or PECVD procedures. at a thickness between about 200 to 2000 Angstroms.
Claim 19
Dependent Claim
46 words
The method of claim 12, wherein said silicon nitride islands are formed via an anisotropic RIE procedure, applied to said second silicon nitride layer, using a fluorine based gas, such as CH 3 F, CHF 3 , or CH 2 F 2 , as an etchant.
Claim 20
Dependent Claim
19 words
The method of claim 12, wherein said narrow space, between said silicon nitride islands, is at least 500 Angstroms.
Claim 21
Dependent Claim
27 words
The method of claim 12, wherein said third silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 3000 to 15000 Angstroms.
Claim 22
Dependent Claim
45 words
The method of claim 12, wherein said selective, first RIE procedure, used to create said wide diameter opening, in said third silicon oxide layer, and to create said narrow diameter opening, in said second silicon oxide layer, is performed using CHF 3 as an etchant.
Claim 23
Dependent Claim
26 words
The method of claim 12, wherein the diameter of said wide diameter opening, in said third silicon oxide layer, is between about 1500 to 10000 Angstroms.
Claim 24
Dependent Claim
26 words
The method of claim 12, wherein the diameter of said narrow diameter opening, in said second silicon oxide layer, is between about 1500 to 5000 Angstroms.
Claim 25
Dependent Claim
70 words
The method of claim 12, wherein said selective, second RIE procedure, used to remove said portion of said silicon nitride, exposed in said wide diameter opening, and used to remove the portion of said first silicon nitride layer, exposed at the bottom of said narrow diameter opening, is performed using a fluorine based such as CHF 3 , CH 2 F 2 , or CH 3 F, as an etchant.
Claim 26
Dependent Claim
44 words
The method of claim 12, wherein said metal structure, formed in said dual damascene opening, is comprised of a titanium -titanium nitride, adhesive--barrier layer, on the sides of said dual damascene opening, and comprised of a copper layer, located inside the dual damascene opening.
References Cited (Backward Citations)
US5612254A
Cited
US5739579A
Cited
US5635423A
Cited
US5686354A
Cited
US5753967A
Cited
US5723387A
Cited
US6028362A
Cited
US6033977A
Cited
US6001414A
Cited
US5935762A
Cited
US6025226A
Cited
US5989997A
Cited
US6027994A
Cited
US6001733A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-25 | 2004-01-24 | 2004-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-25 | 2008-01-24 | 2008-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-25 | 2012-01-24 | 2012-07-25 | $7700.00 | Window Closed / Lapsed |